{"id":11261,"date":"2015-01-14T10:34:26","date_gmt":"2015-01-14T17:34:26","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11261"},"modified":"2026-03-27T08:35:35","modified_gmt":"2026-03-27T12:35:35","slug":"who-knew-vip","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2015\/01\/14\/who-knew-vip\/","title":{"rendered":"Who Knew VIP?"},"content":{"rendered":"

\u201cWho Knew?\u201d about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18.\u00a0 More specifically the article states, \u201cWho knew VIP was big and that Wally had a good piece of it?\u201d\u00a0 We knew.<\/p>\n

We knew that ASIC and FPGA design engineers can choose to buy design IP from several alternative sources or build their own, but that does not help with the problem of verification.\u00a0 We knew that you don\u2019t really want to rely on the same source that designed your IP, to test it.\u00a0 We knew that you don\u2019t want to write and maintain bus functional models (BFMs) or more complete VIP for standard protocols.\u00a0 Not that you couldn\u2019t, but why would you if you don\u2019t have to?<\/p>\n

We also knew that verification teams want easy-to-use VIP that is built on a standard foundation of SystemVerilog, compliant with a protocol\u2019s specification, and is easily configurable to your implementation.\u00a0 That way it integrates into your verification environment just as easily as if you had built it yourself.<\/p>\n

Leading design IP providers such as ARM\u00ae, PLDA, and Northwest Logic knew that Mentor Graphics\u2019 VIP is built on standards, is protocol compliant, and is easy to use.\u00a0 In fact you can read more about what Jim Wallace, systems and software group director at ARM; Stephane Hauradou, CTO of PLDA; and Brian Daellenbach, president of Northwest Logic; have to say about Mentor Graphics\u2019 recently introduced EZ-VIP technology for PCIe 4.0 (at this website http:\/\/www.mentor.com\/company\/news\/mentor-verification-ip-pcie-4<\/a> ), and why they know that their customers can rely on it as well.<\/p>\n

Verification engineers knew, too.\u00a0 You can read comments from many of them (at Cooley\u2019s website http:\/\/www.deepchip.com\/items\/dac14-06.html<\/a> ), about their opinions on VIP.\u00a0 In addition, Mercury Systems also knew.\u00a0 \u201cMentor Graphics PCIe VIP is fully compliant with the PCIe protocol specification and with UVM coding guidelines. We found that we could drop it into our existing environment and get it up and running very quickly\u201d, said Nick Solimini, Consulting DV Engineer at Mercury Systems. \u201cMentor\u2019s support for their VIP is excellent. All our technical questions were answered promptly so we were able to be productive throughout the project\u201d.<\/p>\n

So, now you know,\u00a0 Mentor Graphics\u2019 Questa VIP is built on standard SV UVM, is specification compliant, is easy to get up and running and is an integral part of many successful verification environments today.\u00a0 If you\u2019d like to learn more about Questa VIP and Mentor Graphics\u2019 EZ-VIP technology, send me an email, and I\u2019ll let you in on what (thanks to Cooley and our customers) is no longer the best kept secret in verification.\u00a0 Who knew?<\/p>\n","protected":false},"excerpt":{"rendered":"

\u201cWho Knew?\u201d about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18.\u00a0…<\/p>\n","protected":false},"author":71600,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[409,442,506,690,718,787,820,825,835],"industry":[],"product":[],"coauthors":[],"class_list":["post-11261","post","type-post","status-publish","format-standard","hentry","category-news","tag-dac","tag-dvcon","tag-functional-verification","tag-rtl","tag-simulation","tag-uvm","tag-verification-academy","tag-verification-ip","tag-vip"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11261","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71600"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=11261"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11261\/revisions"}],"predecessor-version":[{"id":19773,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11261\/revisions\/19773"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=11261"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=11261"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=11261"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=11261"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=11261"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=11261"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}