{"id":11216,"date":"2014-11-24T13:35:03","date_gmt":"2014-11-24T20:35:03","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11216"},"modified":"2026-03-27T08:40:28","modified_gmt":"2026-03-27T12:40:28","slug":"systemverilog-testbench-debug-are-we-having-fun-yet","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2014\/11\/24\/systemverilog-testbench-debug-are-we-having-fun-yet\/","title":{"rendered":"SystemVerilog Testbench Debug – Are we having fun yet?"},"content":{"rendered":"

SystemVerilog Testbench Debug – Are we having fun yet?<\/strong><\/p>\n

Fun<\/strong><\/p>\n

Debug should be fun. Watching waveforms march by, seeing ERRORS and WARNINGS pop out in a transcript file, tracing drivers back to their source, understanding race conditions between simulators and between source code changes \u2013 and my favorite \u2013 debugging random stability issues. Fun.<\/p>\n

Old School \u2013 logfiles and interactive<\/strong><\/p>\n

Or at least it should be fun. It used to be fun. I\u2019d setup my collection of scripts to run tests and examine logfiles. Push the button and go for coffee or go home. The next day I\u2019d examine log files and figure out what happened. Usually I\u2019d have to jump into interactive simulation and debug on the fly. Set some breakpoints and watch what happened. That was then. My tests and RTL were all Verilog. Life was good. I was in control of what was going on, and could get my head around it.<\/p>\n

New School \u2013 logfiles, interactive and class handles<\/strong><\/p>\n

Fast-forward to today. Still have scripts to run tests. Still have log files. Still push the button and get coffee or go home. Still jump into interactive simulation. Still set breakpoints. But now my tests are SystemVerilog class-based \u2013 usually UVM. My tests are C code. My tests are constrained random tests. Debug just got harder. I can\u2019t fit the whole testbench + RTL into my head at once. I need help.<\/p>\n

Debugging your class based testbench<\/strong><\/p>\n

I prefer to do as much debug as possible in \u201cpost-sim\u201d mode. I want to run simulation and capture as much as possible. Then debug my wavefile and source code. What to do about my SystemVerilog class based testbench? Easy. Capture my classes in the wave database. Show them to me in the wave window.<\/p>\n

<UVM Testbench class hierarchy window and those same classes in the wave window><\/em><\/strong><\/p>\n

\"Wave<\/a>
Wave Window<\/figcaption><\/figure>\n

But that\u2019s not possible. Is it? What IS possible?<\/strong><\/p>\n

What? Objects in the wave database? Yes. Objects and their members in the wave database.<\/p>\n

Examine the values of class member variables in post-sim mode. Use the waveform window for classes and class member variables just like signals.<\/p>\n

What about the handles that are in my classes? Can I chase them to other objects? Yes. Follow class handle \u201cpointers\u201d to other objects \u2013 essentially exploring the OBJECT SPACE that existed at THAT time during simulation. But I\u2019m in post sim!<\/p>\n

Can I see all the sequence items that hit my driver? Yes. How? Just put the driver \u201chandle\u201d into the wave window and \u201copen\u201d it. You can see the virtual interface handle (if you have one). You can see the transactions that went through the driver (the driver did a \u2018get_next_item (t)\u2019 100,000 times!).<\/p>\n

<Transaction handle \u2018t\u2019 from the driver in the wave window, with the driver\u2019s virtual interface><\/em><\/strong><\/p>\n

\"Driver<\/a>
Driver and ‘t’ in Wave Window<\/figcaption><\/figure>\n

In the wave window? Yes. All 100,000 of them? Yes.<\/p>\n

Now I\u2019m having fun again. That\u2019s great. I can see what\u2019s going on inside my objects. In post-sim mode.<\/p>\n

What\u2019s NOT possible?<\/strong><\/p>\n

Will it babysit? No. One thing at a time.<\/p>\n

 <\/p>\n

Are you having fun yet?<\/p>\n

 <\/p>\n

Find more details in Verification Horizons<\/em>\u00a0article –\u00a0Old School vs. New School – Visualizer<\/a>\u00a0<\/strong>and\u00a0<\/strong>on Verification Academy –\u00a0<\/em>Verification and Debug: Old School Meets New School<\/strong>\u00a0<\/a><\/p>\n

You can find all<\/strong> the sessions on New School verification techniques via the following link:<\/p>\n

https:\/\/verificationacademy.com\/seminars\/academy-live<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…<\/p>\n","protected":false},"author":71540,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[383,419,576,751,758,820,847],"industry":[],"product":[],"coauthors":[],"class_list":["post-11216","post","type-post","status-publish","format-standard","hentry","category-news","tag-class-handles","tag-debug","tag-logfiles","tag-systemverilog","tag-testbench","tag-verification-academy","tag-wave-window"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11216","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71540"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=11216"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11216\/revisions"}],"predecessor-version":[{"id":14488,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11216\/revisions\/14488"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=11216"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=11216"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=11216"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=11216"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=11216"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=11216"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}