{"id":11162,"date":"2014-09-11T22:44:11","date_gmt":"2014-09-12T05:44:11","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11162"},"modified":"2026-03-27T08:43:01","modified_gmt":"2026-03-27T12:43:01","slug":"supporting-a-season-of-learning","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2014\/09\/11\/supporting-a-season-of-learning\/","title":{"rendered":"Supporting A Season of Learning"},"content":{"rendered":"

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year when those taking their first steps to learn VHDL, Verilog\/SystemVerilog join the academic \u201cback to school\u201d crowd and those who are using design & verification languages in practice are honing skills at industry events around the world.<\/p>\n

A new academic year has started and the Mentor Higher Education Program (HEP<\/strong><\/a>) is well set to help students at more than 1200 colleges and universities secure access to the same commercial tools and technology used by industry.\u00a0 It is a real win-win when students learn using the same tools they will use after graduating.\u00a0 Early exposure and use means better skilled and productive engineers for employers.<\/p>\n

The functional verification team at Mentor Graphics knows that many students would prefer to have a local copy of ModelSim on their personal computer to do their course work and smaller projects as they learn VHDL or Verilog.\u00a0 To help facilitate that we make the ModelSim PE Student Edition available for download<\/strong><\/a> without charge.\u00a0 More than 10,000 students use ModelSim PE Student Edition around the world now in addition to our commercial grade tools they can access in their university labs.<\/p>\n

For the practicing engineer, the Verification Academy<\/strong><\/a> offers an online community of more than 25,000 design and verification engineers that exchange ideas on a wide variety issues across the numerous standards and methodologies.\u00a0 If you are not a member of the Verification Academy, I recommend you join<\/strong><\/a>.\u00a0 You will also find the Verification Academy at DAC for one-on-one discussions and even more recently Verification Academy Live daylong seminars which came to Austin and which will be in Santa Clara – as of the writing of this blog.\u00a0 There is still time to register<\/strong><\/a> for the Santa Clara event and I invite you to attend.<\/p>\n

As design and verification is global, Accellera<\/strong><\/a> realized that DVCon should explore the needs of the global design and verification engineer population as well.\u00a0 For 2014, DVCon Europe<\/strong><\/a> and DVCon India<\/strong><\/a> were born from an already successful running SystemC User Group events.\u00a0 These user-led conferences will be held so engineers in these areas can more easily come together to share experiences and knowledge to ultimately become more productive.<\/p>\n

Students and practicing engineers alike can benefit from fee-free access to some of the popular IEEE EDA standards. \u00a0 While I don’t think reading them alone is the ultimate way to educate yourself, they make great companions to daily design and verification activities.\u00a0 Accellera has worked with the IEEE to place several EDA standards in the IEEE Standards Association\u2019s \u201cGet<\/strong><\/a>\u2122\u201d program.\u00a0 Almost 16,000 copies of the SystemC standard (1666) and just about the same number of SystemVerilog standards (1800) have been downloaded as of the end of August 2014.\u00a0 Have you download your free copies yet?<\/p>\n