{"id":10760,"date":"2014-02-11T12:40:03","date_gmt":"2014-02-11T19:40:03","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=10760"},"modified":"2026-03-27T08:43:13","modified_gmt":"2026-03-27T12:43:13","slug":"dvcon-2014-standards-on-display","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2014\/02\/11\/dvcon-2014-standards-on-display\/","title":{"rendered":"DVCon 2014: Standards on Display"},"content":{"rendered":"<p><a href=\"http:\/\/dvcon.org\/\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"margin: 0px 8px 0px 0px;border: 0px currentcolor;float: left\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2014\/02\/DVCon-2014-Logo_thumb.png\" alt=\"DVCon 2014 Logo\" width=\"90\" height=\"100\" align=\"left\" border=\"0\" \/><\/a>One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.\u00a0 And this year\u2019s DVCon is no exception.\u00a0 The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.\u00a0 For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers.<\/p>\n<p><a href=\"http:\/\/www.accellera.org\/community\/uvm\/\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"margin: 0px 4px 0px 0px;border: 0px currentcolor;float: right\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2014\/02\/UVM-Logo.jpg\" alt=\"UVM Logo\" width=\"92\" height=\"68\" align=\"right\" border=\"0\" \/><\/a>I have written in the past about the productivity challenges before us to address the <em>verification crisis<\/em> and the emergence of machine-to-machine communication and the <em>Internet of Things<\/em> driving power aware design and verification.\u00a0 To advance the demands on improved verification and help to address the verification crisis, the next round in the Universal Verification Methodology (UVM) standard is being readied for industry adoption.\u00a0 UVM 1.2, the emerging update will be covered in some detail in a Monday morning tutorial to help you learn \u201cWhat\u2019s Now and What\u2019s Next.\u201d\u00a0 Mentor Graphics\u2019 Tom Fitzpatrick and Accellera Working Group representative will present in this tutorial.<\/p>\n<p>UVM 1.2 is an active development project of Accellera and has not yet been released so there is no official standard available for download and use yet.\u00a0 I\u2019ll share standardization details as they happen.<\/p>\n<p><a href=\"http:\/\/go.mentor.com\/IEEE-1801-2013-Standard\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"float: right\" src=\"http:\/\/www.accellera.org\/about\/policies\/logos\/upf_logo.png\" alt=\"\" width=\"98\" height=\"58\" align=\"right\" \/><\/a>At the same time on Monday, those who are concerned with power aware design and verification can attend the tutorial on the Unified Low Power Format (UPF), or as it is officially called IEEE 1801\u2122-2013.\u00a0 The tutorial will cover the full spectrum of UPF capabilities and methodology from basic to advanced applications.\u00a0 So if you are new to UPF and want to learn, this is a great tutorial to attend.\u00a0 And if you are already an expert, the advanced application of UPF as highlighted by those companies who have adopted UPF make this valuable for you as well.\u00a0 Mentor Graphics\u2019 Erich Marschner and IEEE 1801 Working Group vice-chair will participate in this tutorial.<\/p>\n<p>UPF is an official IEEE standard.\u00a0 Have you downloaded your copy yet?\u00a0 Accellera has worked with the IEEE to make no-charge access to the official standard for you.\u00a0 You can find the UPF standard <a href=\"http:\/\/go.mentor.com\/IEEE-1801-2013-Standard\" target=\"_blank\" rel=\"noopener\">here<\/a>.<\/p>\n<p><a href=\"http:\/\/go.mentor.com\/SystemCStandard\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"float: right\" src=\"http:\/\/www.accellera.org\/about\/policies\/logos\/logo_systemc.gif\" alt=\"\" width=\"105\" height=\"41\" align=\"right\" \/><\/a>In the afternoon, there will be a session on case studies in SystemC.\u00a0 User and vendor presentations will explore use of this standard.\u00a0 SystemC offers much in the verification space, not just in technology but learning on how to bridge the RTL world with transaction level modeling world.\u00a0 Mentor Graphics\u2019 John Stickley will review what we have learned and how you can apply it to your most pressing verification needs.<\/p>\n<p>SystemC is an official IEEE standard.\u00a0 Have you downloaded your copy yet?\u00a0 Under the Accellera agreement with the IEEE, you can download SystemC standard <a href=\"http:\/\/go.mentor.com\/SystemCStandard\" target=\"_blank\" rel=\"noopener\">here<\/a>.<\/p>\n<p>There is a lot more to DVCon than just the use of current standards and planning adoption of emerging standards.\u00a0 I encourage you to check out the whole <a href=\"http:\/\/dvcon.org\/\" target=\"_blank\" rel=\"noopener\">agenda<\/a> and join me at DVCon 2014 March 3-6.<\/p>\n<p>Mentor Graphics presentations during the conference include:<\/p>\n<ul>\n<li><strong><span>Tuesday Paper Sessions<\/span><\/strong><\/li>\n<ul><!--StartFragment--><\/p>\n<li><strong>Amit Srivastava<\/strong> \u2013 Stepping Into UPF 2.1 World: Easy Solution to Complex<br \/>\nPower Estimation<\/li>\n<li><strong>Kenneth Bakalar<\/strong> &#8211; Interpreting UPF For A Mixed-Signal Design Under Test<\/li>\n<li><strong>Gordon Allan<\/strong> \u2013 Tried and Tested Speedups for Software-Driven SoC Simulatio<\/li>\n<\/ul>\n<li><strong><span>Tuesday Poster Sessions<\/span><\/strong><\/li>\n<ul><!--StartFragment--><\/p>\n<li><strong>Rich Edelman<\/strong> \u2013 Debugging Communicating Systems: The Blame Game \u2013 Blurring<br \/>\nthe Line Between Performance Analysis and Debug<\/li>\n<li><strong>Matthew Balance<\/strong> \u2013 Tackling Random Blind Spots with Strategy-Driven Stimulus Generation<\/li>\n<li><strong>Gaurav K. Verma<\/strong> \u2013 Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC\/DC-Compliant Coverage Methodology<\/li>\n<li><strong>Andreas Meyer<\/strong> \u2013 So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results<\/li>\n<li><strong>Rich Edelman<\/strong> \u2013 UVM SchmooVM \u2013 I Want My C Tests!<\/li>\n<li><strong>Thom Ellis<\/strong> \u2013 Are\u00a0 You Really Confident That You Are Getting the Very Best From Your Verification Resources?<\/li>\n<li><strong>Jitesh Bansal<\/strong> \u2013 Is Your Power Aware Design Really X-Aware<\/li>\n<\/ul>\n<li><strong><span>Wednesday Paper Sessions<\/span><\/strong><\/li>\n<ul>\n<li><strong>Avidan Efody<\/strong> \u2013 Wiretap Your SoC: Why Scattering Verification IPs Throughout Your Design Is A Smart Thing To Do<\/li>\n<li><strong>Tom Fitzpatrick<\/strong> \u2013 Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It<\/li>\n<\/ul>\n<\/ul>\n<p>Mentor Graphics will host its traditional lunch at DVCon on Wednesday on the theme of Accelerating Verification.\u00a0 And we have lively panel participants for the Tuesday and Wednesday panels.\u00a0 And, as always, the Exhibit, CEO Keynote and Panels are open to all a no charge \u2013 you just have to <a href=\"http:\/\/dvcon.org\/content\/rates\" target=\"_blank\" rel=\"noopener\">REGISTER<\/a>!<\/p>\n<p>I look forward to seeing you there!<\/p>\n","protected":false},"excerpt":{"rendered":"<p>One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera&#8230;<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[442,535,732,749,785,787],"industry":[],"product":[],"coauthors":[],"class_list":["post-10760","post","type-post","status-publish","format-standard","hentry","category-news","tag-dvcon","tag-ieee-1801","tag-standards","tag-systemc","tag-upf","tag-uvm"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10760","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=10760"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10760\/revisions"}],"predecessor-version":[{"id":14606,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10760\/revisions\/14606"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=10760"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=10760"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=10760"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=10760"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=10760"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=10760"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}