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My personal favorite is scheduled for Halloween Day at 1:30pm, where I\u2019ll tell you about a trick that Altera used to shave several months off their schedule, while verifying the functionality and performance of an ARM AXI\u2122 fabric interconnect subsystem.\u00a0 And the real treat is that they achieved first silicon success as well.\u00a0 In keeping with the event\u2019s theme, they used something called \u201cintelligent\u201d testbench automation.<\/p>\n
And whether you\u2019re designing multi-core designs with AXI fabrics, wireless designs with AMBA\u00ae 4 ACE\u2122 extensions, or even enterprise computing systems with ARM\u2019s latest AMBA\u00ae 5 CHI\u2122 architecture, these sessions show you how to take advantage of the very latest simulation and formal technology to verify SoC connectivity, ensure correct interconnect functional operation, and even analyze on-chip network performance.<\/p>\n
On Tuesday at 10:30am, Gordon Allan described how an intelligent performance analysis solution can leverage the power of an SQL database to analyze and verify interconnect performance in ways that traditional verification techniques cannot.\u00a0 He showed a wide range of dynamic visual representations produced by SoC regressions that can be quickly and easily manipulated by engineers to verify performance to avoid expensive overdesign.<\/p>\n
Right after Gordon\u2019s session, Ping Yeung discussed using intelligent formal verification to automate SoC connectivity, overcoming observability and controllability challenges faced by simulation-only solutions.\u00a0 Formal verification can examine all possible scenarios exhaustively, verifying on-chip bus connectivity, pin multiplexing of constrained interfaces, connectivity of clock and reset signals, as well as power control and scan test signal connectivity.<\/p>\n
On Wednesday, Mark Peryer shows how to verify AMBA interconnect performance using intelligent database analysis and intelligent testbench automation for traffic scenario generation.\u00a0 These techniques enable automatic testbench instrumentation for configurable ARM-based interconnect subsystems, as well as highly-efficient dense, medium, sparse, and varied bus traffic generation that covers even the most difficult to achieve corner-case conditions.<\/p>\n
And finally also on Halloween, Andy Meyer offers an intelligent workshop for those that are designing high performance systems with hierarchical and distributed caches, using either ARM\u2019s AMBA 5 CHI architecture or ARM\u2019s AMBA 4 ACE architecture.\u00a0 He\u2019ll cover topics including how caching works, how to improve caching performance, and how to verify cache coherency.<\/p>\n