{"id":10352,"date":"2013-10-15T15:02:43","date_gmt":"2013-10-15T22:02:43","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=10352"},"modified":"2026-03-27T08:43:18","modified_gmt":"2026-03-27T12:43:18","slug":"ieee-standards-association-symposium-on-eda-interoperability","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2013\/10\/15\/ieee-standards-association-symposium-on-eda-interoperability\/","title":{"rendered":"IEEE Standards Association Symposium on EDA Interoperability"},"content":{"rendered":"<h2><span>Low Power Flow Kicks-off Symposium<\/span><\/h2>\n<p>In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition.\u00a0 Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon.\u00a0 The <a href=\"http:\/\/standards.ieee.org\/\" target=\"_blank\" rel=\"noopener\">IEEE Standards Association<\/a> is holding a <a href=\"https:\/\/standards.ieee.org\/events\/edasymposium\/\" target=\"_blank\" rel=\"noopener\">Symposium on EDA Interoperability<\/a> to help members of the electronics\/semiconductor design and verification community better understand the landscape of EDA and IP standards and the role they play to address interoperability.<\/p>\n<p>Another key component are the programs and business relationships we foster to promote tool connectivity and interoperability among each other.\u00a0 The Questa users rely on the <a href=\"http:\/\/www.mentor.com\/products\/fv\/partners\/qvp\" target=\"_blank\" rel=\"noopener\">Questa Vanguard Partnership<\/a> program so their trusted tool and technology partners have access to our verification technology to allow them to craft the leading edge design and verification flows with technology from numerous sources.\u00a0 If your users want you to connect with Questa, we invite them to explore the benefits of this program.\u00a0 Even better, join us at the IEEE SA Symposium on EDA Interoperability where can also discuss this in person \u2013 <a href=\"https:\/\/iecs.memberclicks.net\/index.php?option=com_mc&amp;view=mc&amp;mcid=form_144136\" target=\"_blank\" rel=\"noopener\">Register Here<\/a>!<\/p>\n<p><span><strong>Event Details<\/strong><br \/>\n<\/span><strong>Date:<\/strong> 24 October 2013<br \/>\n<strong>Time:<\/strong> 9:00 a.m. \u2013 6:00 p.m. PT<br \/>\n<strong>Location:<\/strong> Techmart \u2013 5201 Great America Parkway, Santa Clara, CA 95054-1125<br \/>\n<strong>Cost:<\/strong> Free!<br \/>\n<strong>Program: <\/strong><a href=\"http:\/\/standards.ieee.org\/events\/edasymposium\/program.html\" target=\"_blank\" rel=\"noopener\">http:\/\/standards.ieee.org\/events\/edasymposium\/program.html<\/a><\/p>\n<p>One of the more pressing issues in design and verification today is address the issue of low power.\u00a0 The IEEE SA Symposium on EDA kicks-off the morning with its first session on \u201cInteroperability Challenges: Power Management in Silicon.\u201d\u00a0 The session will feature an opening presentation on the state of standardization by the Vice Chair of the IEEE P1801 Working Group (and Mentor Graphics Verification Architect) as well as two presentations from ARM on the use of the IEEE 1801 (<a href=\"http:\/\/standards.ieee.org\/getieee\/1801\/download\/1801-2013.pdf\" target=\"_blank\" rel=\"noopener\">UPF<\/a>) standard.<\/p>\n<table width=\"623\" border=\"0\" cellspacing=\"0\" cellpadding=\"2\">\n<tbody>\n<tr>\n<td valign=\"top\" width=\"22\"><\/td>\n<td valign=\"top\" width=\"164\">11:00 a.m. \u2013 12:00 p.m.<\/td>\n<td valign=\"top\" width=\"435\"><strong>Session 1: Interoperability Challenges: Power Management in Silicon<\/strong><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"22\"><\/td>\n<td valign=\"top\" width=\"164\"><\/td>\n<td valign=\"top\" width=\"435\"><em>IEEE 1801 Low Power Format: Impact and Opportunities<\/em><br \/>\n<strong>Erich Marschner<\/strong>, Vice Chair of IEEE P1801 Working Group, Verification Architect, Mentor Graphics<\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"22\"><\/td>\n<td valign=\"top\" width=\"164\"><\/td>\n<td valign=\"top\" width=\"435\"><em>Power Intent Constraints: Using IEEE1801 to improve the quality of soft IP<br \/>\n<\/em><strong>Stuart Riches<\/strong>, Project Manager, ARM<\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"22\"><\/td>\n<td valign=\"top\" width=\"164\"><\/td>\n<td valign=\"top\" width=\"435\"><em>Power Intent Verification: Using IEEE1801 for the verification of ARM Cortex A53 processor<\/em><br \/>\n<strong>Adnan Khan<\/strong>, Senior Engineer, ARM<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The event is sponsored by Mentor Graphics and Synopsys and we have made sure the symposium is free to attend.\u00a0 You just need to register.\u00a0 There are other great aspects to the event, not just the ability to have a conversation on the state of standards for low power design and verification in the morning.\u00a0 In fact, the end of the event will take a look at EDA 2020 and what is needed in the future.\u00a0 This will be a very interactive session that will open the conversation to all attendees.\u00a0 I can\u2019t wait to learn what you have to share!\u00a0 See you at the Techmart on the 24th.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its&#8230;<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[342,535,539,554,577,672,732,785],"industry":[],"product":[],"coauthors":[],"class_list":["post-10352","post","type-post","status-publish","format-standard","hentry","category-news","tag-arm","tag-ieee-1801","tag-ieee-standards-association","tag-interoperability","tag-low-power","tag-questa-vanguard-partnership","tag-standards","tag-upf"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10352","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=10352"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10352\/revisions"}],"predecessor-version":[{"id":14608,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/10352\/revisions\/14608"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=10352"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=10352"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=10352"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=10352"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=10352"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=10352"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}