Equivalence Checking

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The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

February 2, 2022

With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many…

By Joe Hupcey III
4 MIN READ

The Many Flavors of Equivalence Checking: Part 5, Summary of the Most Popular LEC and SLEC Use Cases

July 13, 2020

As I noted at the beginning of this series, the term “logic equivalence checking” (LEC) applies to a number of…

By Joe Hupcey III
4 MIN READ

The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification

May 19, 2020

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, Part 2 describes how…

By Joe Hupcey III
4 MIN READ

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

March 23, 2020

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

By Joe Hupcey III
4 MIN READ

The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

August 20, 2019

Perhaps the only Sequential Logic Equivalence Checking (SLEC) flow that is as common as the synthesis validation flow described in…

By Joe Hupcey III
3 MIN READ
The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

July 11, 2019

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

By Joe Hupcey III
5 MIN READ