Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

Logging in pyuvm

Logging in pyuvm This is part of the Python for Verification series of blog posts. The IEEE UVM specification (1800.2-2020)…

The UVM Factory

In the previous post in the Python for Verification Series, we discussed how pyuvm implemented the configuration database as a…

The configuration database in pyuvm

The configuration database In the previous post in the Python for Verification Series we discussed how pyuvm implemented TLM 1.0….

TLM 1.0 in pyuvm

This blog post is part of a continuing series discussing Python as a verification language. You can find links to…

Python and the UVM

In our previous two posts in this series on Python as a verification language, we examined Python coroutines and using…

TinyALU and its BFMs

Cocotb Bus Functional Models

In this series we’re talking about using Python as the testbench software in this testbench diagram: The testbench software uses…

Proxy-Testbench

Introduction to Coroutines

In the first post of this series on Python verification we discussed the proxy-driven testbench and how a proxy-driven architecture…

Proxy-driven testbench

Verification Learns a New Language

Abraham Lincoln once said, “What is conservatism? Is it not adherence to the old and tried, against the new and…