Mitigating Security Risks When Designing with 3rd-Party Silicon IP

Accellera DAC Panel to Discuss

There is probably not one embedded system that is not built without open source software, 3rd party silicon IP or manufactured far from the design and distribution centers that make and sell these systems.  Those who want to secure the design and delivery chain have no standard to use to address this.  This has left develop teams to struggle with means to mitigate and address security risks when third party IP and associated components are integrated into today’s modern embedded systems.

There are many conferences devoted to security related issues and we have all read about Meltdown and Spectre, I suspect.  There are some security risks which may not have gotten extensive global attention like A2 which is an analog attack exploiting an almost hidden capacitor.  The Electronic Design Automation industry has even had exploits documented in conference papers that show how encrypted design and verification IP can be made visible, for which the standards team is now hard at work to address.

And for embedded systems we have accepted a certain level of risk when it comes to integrating third-party IP into our SoC devices.  Modern SoC designs gain productivity leverage when they can be designed with silicon IP that comes from multiple sources, from sources that have expertise in those particular blocks.  Who do you use and trust for your memory controllers, protocol interface handlers and the like?  In order to build the best SoC, we seek out the highest quality silicon IP to be part of our SoC’s.

Are these high quality silicon IP’s free of exploits?  Have they arrived for integration into your SoC without being tampered?  What level of assurance do you have they are safe and clean?  You may have the source, but when SoC integrators use the blocks, they are most likely treated as a black-boxes and not heavily vetted for compromise.

To help address these issues, Accellera’s newest working group, the IP Security Assurance Working Group was formed.  To share more with the design automation and IP community, Accellera is hosting a luncheon on Monday at the 56th Design Automation Conference with a panel of industry experts to address these issues and more.  You are invited to attend!

Accellera DAC IP Security Assurance Luncheon & Panel Event Details

Join panelists from Analog Devices, DARPA, Intel and Tortuga Logic for a lively discussion.  The luncheon is free for DAC  attendees, but registration with Accellera is required.

Monday, June 3rd
Noon – 1:30pm
Room N246, Las Vegas Convention Center
Registration and more information: Click Here

I look forward to seeing you there!