When it comes to profitability in the electronics manufacturing sector, we talk a lot about mitigating risks by performing design verification and discovering flaws during the board design phase. It\u2019s clear that errors become costlier to fix as the project progresses. Can the same be said about errors in the test infrastructure of PCBs?<\/p>\n\n\n\n
If you are an experienced PCB designer, you\u2019ve surely been surprised by a net lacking test coverage, or by a test point that is blocked by an adjacent component, preventing access. Flaws such as these \u2013 which affect the manufacturability of your design \u2013 are usually identified by a test engineer during the Design for Test (DFT) analysis<\/a>, which typically occurs late in the layout process, making the flaws costly to remediate. In addition, the analysis is manual and doesn\u2019t scale well.<\/p>\n\n\n\n Wouldn\u2019t it be more efficient if DFT could be analyzed by anyone in the design flow \u2013 as early as in the schematic capture or design phases \u2013 by putting advanced test strategy tools in the hands of designers? In the fourth session<\/a> of our series of 12 mini-webinars on Implementing \u201cDigital Twin\u201d Best Practices From Design Through Manufacturing<\/em><\/a>, we focus on on design verification from a testing point of view<\/strong>.<\/p>\n\n\n\n By improving the testability of PCBs early in the design process, we save money by avoiding scenarios like the one mentioned above, and drastically reduce the number of required re-spins. In this way, we can further implement the digital-twin strategy that \u201cleft-shifts\u201d crucial processes and decisions, and help organizations get it right the first time.<\/p>\n\n\n\n