{"id":733,"date":"2019-07-24T09:41:29","date_gmt":"2019-07-24T16:41:29","guid":{"rendered":"http:\/\/blogs.mentor.com\/tessent\/?p=733"},"modified":"2026-03-26T16:07:43","modified_gmt":"2026-03-26T20:07:43","slug":"dft-architectural-tips-testing-of-asynchronous-sets-resets","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/tessent\/2019\/07\/24\/dft-architectural-tips-testing-of-asynchronous-sets-resets\/","title":{"rendered":"DFT architectural tips: testing of asynchronous sets\/resets"},"content":{"rendered":"\n

Most designs have some asynchronous sets or resets. Uncontrollable sets\/resets can lower test coverage. This video discusses how to handle asynchronous sets\/resets and how to test hierarchical blocks independently even if they have a common source.<\/em><\/p>\n\n\n\n\n\n\n

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To manage asynchronous sets\/resets, designers add control logic. But first, the sets\/resets need to be defined at the RTL or gate-level and then evaluated through DRC checks to learn if the asynchronous sets\/resets can be controlled. Sometimes, they need to be disabled during test. Tessent users can control the override of the sets\/resets with test data registers via an IJTAG network.<\/p>\n\n\n\n

The sets\/resets need to be disabled during shift, and enabled during capture.  In this video, Vidya Neerkundar describes the DFT logic that can be used to disable and enable sets\/resets.<\/p>\n\n\n\n

Within a chip, there may be hierarchical regions (or blocks, or cores) with asynchronous sets\/resets. If they are at the boundary of a physical layout region, dedicated wrapper cells are inserted to control those sets\/resets. Neerkundar describes how this core-level set\/reset control aids in testing multiple cores at different times, independently of other blocks or parent levels.<\/p>\n\n\n\n

If you are looking for tips on how to better handle asynchronous sets\/resets to improve test coverage, we recommend watching Neerkundar’s short video.<\/p>\n\n\n\n

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