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What is VersaPoint\u2122? It is a new type of test point that allows users to target both ATPG pattern count reduction and LBIST test coverage improvements in a single test point insertion pass. Why is this important? Because of the rapid adoption, especially among mission-critical ICs used for automotive applications, of a Hybrid ATPG\/logic built-in self-test (LBIST) strategy. The once-separate ATPG and LBIST technologies have merged to the point where compression IP is being re-used to apply BIST tests. The result is smaller test sets, higher fault coverage, and the integration of self-test required by the functional safety standard ISO 26262.<\/p>\n Test points are dedicated design structures used to improve the test results. Traditional LBIST test points improve results by addressing random pattern resistance in ICs. Mentor previously developed test points specifically for on-chip compression\/ATPG, which reduces ATPG pattern count by 2-4X above what is achieved with on-chip compression alone.<\/p>\n However, if you have a Hybrid ATPG\/LBIST methodology, don\u2019t you also want a more efficient test point insertion strategy? That\u2019s where VersaPoint\u2122 test point technology comes in; it combines and improves upon previous test point algorithms.<\/p>\n Say you get 46X compression with Tessent TestKompress, why not go for an additional 2-4X on top of that, which is what we\u2019ve seen in experiments using VersaPoint technology on industrial designs. VersaPoint\u2122 test points work with Hybrid ATPG\/LBIST with more efficiency than test points for either ATPG or LBIST separately. Test points that target both scan compression and BIST significantly cut test time and cost with no loss of coverage.<\/p>\n To learn a lot more about VersaPoint\u2122 technology, download this new whitepaper, Improving Test Pattern Compression with Tessent VersaPoint Test Point Technology<\/a>. This paper explains how VersaPoint\u2122 test points work and includes experimental data from industrial designs demonstrating pattern count reduction with VersaPoint\u2122 technology.<\/p>\n![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/48\/2017\/12\/JF_Versapoint_fig-1.jpg\")
<\/a>There is no escaping the trends in the semiconductor industry that lead to increased IC test data volumes, longer test application times, and higher test costs. But, there are new strategies and technologies to manage these challenges to the bottom line. The latest boost to reducing test data sets is VersaPoint\u2122 test point technology.<\/p>\n