{"id":2288,"date":"2026-03-23T12:24:30","date_gmt":"2026-03-23T16:24:30","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/tessent\/?p=2288"},"modified":"2026-03-26T16:08:18","modified_gmt":"2026-03-26T20:08:18","slug":"detect-diagnose-and-debug-using-sensors-and-functional-monitoring","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/tessent\/2026\/03\/23\/detect-diagnose-and-debug-using-sensors-and-functional-monitoring\/","title":{"rendered":"Detect, diagnose, and debug using sensors and functional monitoring"},"content":{"rendered":"\n
Co-authors: Movellus and Siemens EDA<\/h3>\n\n\n\n
Modern AI workloads drive an extremely “spiky” power profile where current demands surge to hundreds of Amps within nanoseconds, clashing with the tighter operating ranges of advanced process nodes as they push below 0.8V. This creates a physical bottleneck: the on-die power delivery network (PDN) cannot sustain the instantaneous current required by complex AI workloads, effectively capping computational throughput. Consequently, performance is no longer limited by transistor switching speeds but by the instability of the voltage supply under the stress of high-coincidence-matrix operations.<\/p>\n\n\n\n
The scale of this challenge has grown considerably. Rack-level power density has increased from a few kilowatts in traditional enterprise deployments and is quickly growing towards over 100kW in modern AI-optimized configurations. GPU-based AI accelerators cycle through millisecond-scale execution phases \u2014 prefill (loading and processing the input prompt), decode (generating each output token), and idle \u2014 each with distinct performance, thermal, and power characteristics. These transitions produce load transients with low inertia, significant surges and dips, and a high peak-to-idle ratio that conventional power delivery infrastructure was not designed to handle.<\/p>\n\n\n\n
Planning for these workloads is extremely difficult because they are transient (both instructional and data-dependent), often manifesting only as intermittent functional failures or throughput degradation that evades standard verification, characterization, and system-level testing methodologies. Because the relationship between instruction sequences, data patterns, and voltage is unpredictable, these failures are nearly impossible to observe or model with legacy tools. This forces chip and system designers into a costly trade-off: accept efficiency losses from excessive guard banding \u2014 the voltage safety margin added at design time to absorb worst-case transients \u2014 or face the risk of undetected errors at scale. With multi-hundred-billion-dollar investment flowing into AI-centric datacentres over the coming years, having the ability to observe and correlate physical PDN changes with functional behavior is essential at fleet scale.<\/p>\n\n\n\n
Achieving this requires two capabilities working in concert: visibility into on-chip workload behavior, and real-time voltage telemetry at the transistor level.<\/p>\n\n\n\n
Siemens Tessent Embedded Analytics addresses the first, and Movellus Aeonic Insight the second.<\/strong><\/p>\n\n\n\n
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Functional and Physical Monitors<\/strong><\/h2>\n\n\n\n
Siemens EDA Tessent Embedded Analytics provides a suite of functional monitors that observe on-chip behavior without interrupting normal device operation. The monitors capture workload activity at the core and interconnect level and can be configured to focus on specific conditions \u2014 filtering trace data to what is relevant for a given workload. A key capability is cross-triggering: the monitors can record a window of activity both before and after a trigger event occurs, giving engineers the context needed to understand what led to a failure or performance anomaly. What functional data alone cannot capture is the voltage behavior driving those anomalies \u2014 that requires direct measurement at the transistor level.<\/p>\n\n\n\n
Movellus Aeonic Insight Droop Detector monitors on-die voltage continuously and generates a hardware trigger when voltage crosses a programmed threshold. Telemetry from the detector such as voltage levels and edge analytics including watermark values and averaging is readable in real time, making it possible to correlate voltage events directly with the workload conditions that caused them.<\/p>\n\n\n\n
Siemens and Movellus built a demonstration system on a AMD Zynq\u2122 UltraScale+\u2122 (Figure 1) in which two RISC-V cores run the target workload, with Tessent Embedded Analytics Bus Monitor monitoring\u00a0\u00a0\u00a0\u00a0 transaction traffic across the SoC interconnect, and Movellus Droop Detector IP monitoring the on-die voltage using the Tessent Embedded Analytics Status Monitor. When the Droop Detector senses a voltage transient crossing a programmed threshold, it fires a hardware trigger to the Embedded Analytics infrastructure \u2014 which captures a snapshot of both core execution state and interconnect activity at the moment the voltage event occurred.\u00a0<\/p>\n\n\n\n
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\n<\/figure><\/div>\n\n\n
Figure 1: FPGA demo\u00a0– RISC-V cores and Droop Detector connected to EA infrastructure, including Status Monitor (SM) and Bus Monitor (BM)<\/h4>\n\n\n\n
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\n<\/figure><\/div>\n\n\n
Figure 2: Voltage event correlated with workload<\/h4>\n\n\n\n
Figure 2 shows time-aligned traces of workload activity\u00a0 (bus usage) and on-die voltage \u2014 the two data streams the demo captures simultaneously. The voltage droops correspond directly to peaks in workload intensity, with each threshold crossing marking the moment the Embedded Analytics snapshot\u00a0 starts collecting data This time-aligned view is what transforms raw telemetry into a diagnostic tool: rather than knowing only that voltage stress occurred, engineers can see precisely which workload conditions drove it, where it occurred, and at what severity. At scale, that specificity is the difference between applying guard bands uniformly and calibrating them to the conditions that actually matter.<\/p>\n\n\n\n
<\/div>\n\n\n\n
In Conclusion <\/h2>\n\n\n\n
When on-chip functional observability and real-time voltage telemetry work in concert, the relationship between workload behavior and PDN stress becomes traceable rather than inferred. For chip designers, this means calibrating guard bands to the specific instruction sequences and workload conditions that drive voltage excursions \u2014 not to worst-case assumptions. For fleet operators, it means telemetry granular enough to make workload decisions grounded in measured PDN data. Together, that translates into tighter operating margins, reduced efficiency losses, and AI infrastructure optimized to run closer to its physical limits.<\/p>\n\n\n\n
Discover how a Tessent functional monitoring solution, working in conjunction with Movellus Inc. Aeonic Insight\u2122 Droop Detector IP for Power Delivery Network (PDN) telemetry, can provide a multi-instrument monitoring solution that detects a voltage anomaly, and cross-triggers functional monitoring that enables engineers to diagnose issues. <\/p>\n
This combined approach provides enhanced visibility and insight, as part of Silicon Lifecycle Management and delivers a more sophisticated approach to monitoring, in order to detect and perform root-cause analysis in-life. <\/p>\n","protected":false},"author":87226,"featured_media":2291,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[775],"tags":[370,786,787,788,750,398,357],"industry":[55,53,56,57],"product":[629],"coauthors":[719],"class_list":["post-2288","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blogs","tag-embedded-analytics","tag-movellus","tag-movellus-aeonic","tag-movellus-aeonic-insight","tag-risc-v","tag-system-on-chip","tag-tessent","industry-electronic-manufacturing-services","industry-electronics-semiconductors","industry-semiconductor-devices","industry-semiconductor-equipment","product-tessent-embedded-analytics"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/48\/2026\/03\/Fig-1-FPGA-demo.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/2288","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/users\/87226"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/comments?post=2288"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/2288\/revisions"}],"predecessor-version":[{"id":2299,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/2288\/revisions\/2299"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/media\/2291"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/media?parent=2288"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/categories?post=2288"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/tags?post=2288"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/industry?post=2288"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/product?post=2288"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/coauthors?post=2288"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
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