{"id":2159,"date":"2024-01-16T19:30:21","date_gmt":"2024-01-17T00:30:21","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/tessent\/?p=2159"},"modified":"2026-03-26T16:08:05","modified_gmt":"2026-03-26T20:08:05","slug":"leveraging-the-risc-v-efficient-trace-e-trace-standard","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/tessent\/2024\/01\/16\/leveraging-the-risc-v-efficient-trace-e-trace-standard\/","title":{"rendered":"Video: Leveraging the RISC-V efficient trace (E-Trace) standard"},"content":{"rendered":"\n

Understanding program behavior in complex systems is not easy. Understanding the behavior of complete systems is even more challenging. Get non-intrusive, full-speed and system-level visibility with E-Trace.<\/em><\/p>\n\n\n\n

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Processor trace gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. Efficient Trace for RISC-V (E-Trace) was the topic of a well-attended presentation at the RISC-V Summit held on November 7-8 in Santa Clara, CA. Iain Roberston, Senior Director of hardware engineering in the Tessent group at Siemens EDA delivered \u201cLeveraging the RISC-V efficient trace (E-Trace) standard.\u201d His 17-minute presentation was recorded and is now available on-demand.<\/p>\n\n\n\n

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What you\u2019ll learn:<\/p>\n\n\n\n