{"id":1999,"date":"2023-06-26T14:04:23","date_gmt":"2023-06-26T18:04:23","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/tessent\/?p=1999&#038;preview=true&#038;preview_id=1999"},"modified":"2026-03-26T16:07:34","modified_gmt":"2026-03-26T20:07:34","slug":"video-system-on-chip-atpg-with-tessent-ssn","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/tessent\/2023\/06\/26\/video-system-on-chip-atpg-with-tessent-ssn\/","title":{"rendered":"Video: System-on-chip ATPG with Tessent SSN"},"content":{"rendered":"\n<p class=\"has-medium-font-size\">At the 2023 North America User2user symposium, Intel engineer Toai Vo presented his team&#8217;s experience using Tessent Streaming Scan Network (SSN).  The session was recorded and is now available for anyone to view.<\/p>\n\n\n\n<p>Toia covers their test challenges, what led them to Tessent SSN, and how they successfully completed their first silicon design using Tessent SSN. <\/p>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"System on Chip ATPG with Tessent Streaming Scan Network (SSN) - INTEL\" width=\"640\" height=\"360\" src=\"https:\/\/www.youtube.com\/embed\/scQnXdyVLXc?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p>Toia&#8217;s team needed a tool and flow that would help with ATPG automation, reusability, reducing test cost, effort and time, and would also support 2.5\/3D test methodology. Tessent SSN, the bus-based packetized test solution, addresses all their challenges. Tessent SSN is highly scalable and has a test infrastructure that enables reuse across device families.<\/p>\n\n\n\n<blockquote class=\"wp-block-quote is-layout-flow wp-block-quote-is-layout-flow\">\n<p>With SSN, you only need to decide the data bus size at the chip level. You don&#8217;t have to worry about what&#8217;s inside the blocks. SSN is absolutely an innovative test solution. It really works!<\/p>\n<cite>Toai Vo, Intel<\/cite><\/blockquote>\n\n\n\n<p>Toia&#8217;s group at Intel also liked that SSN uses the IEEE 1687 (IJTAG) network, allows easy retargeting of test patterns from block-level to chip-level, that the SSN test logic is inserted at RTL, that any number blocks can be tested concurrently to save test time. <\/p>\n\n\n\n<p>Toai shared the results of the first silicon tests using SSN. They report a significant reduction in total test time of about 34%. Toai says the transition from traditional EDT to packet-based SSN was easy. The solution is scalable, reusable, reduces test time, and improves productivity by reducing engineering effort and silicon bring up time.  <\/p>\n\n\n\n<p>Learn more about Tessent SSN in this on-demand webinar <strong><a href=\"https:\/\/event.on24.com\/wcc\/r\/4133826\/90B8AE87E6087F3C5C50F7CC39F34588?partnerref=blog\" target=\"_blank\" rel=\"noreferrer noopener\">Automation and plug-and-play DFT methods for fast time-to-market<\/a><\/strong>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Learn how Intel adopted Tessent SSN packet-based ATPG and reduced test time by 34% in this video recorded at the 2023 North America U2U symposium.<\/p>\n","protected":false},"author":69877,"featured_media":1705,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[7,1],"tags":[308,700,724],"industry":[53,56],"product":[269,683],"coauthors":[719],"class_list":["post-1999","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-learning-resources","category-news","tag-atpg","tag-ssn","tag-ssn-streaming-scan-network","industry-electronics-semiconductors","industry-semiconductor-devices","product-tessent","product-tessent-test"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/48\/2022\/10\/SSN-web-image-1280x720-1-scaled.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/1999","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/users\/69877"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/comments?post=1999"}],"version-history":[{"count":2,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/1999\/revisions"}],"predecessor-version":[{"id":2004,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/posts\/1999\/revisions\/2004"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/media\/1705"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/media?parent=1999"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/categories?post=1999"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/tags?post=1999"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/industry?post=1999"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/product?post=1999"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/tessent\/wp-json\/wp\/v2\/coauthors?post=1999"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}