{"id":92,"date":"2022-08-29T17:56:58","date_gmt":"2022-08-29T21:56:58","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=92"},"modified":"2026-03-27T09:09:59","modified_gmt":"2026-03-27T13:09:59","slug":"3d-ic-verification-requires-a-golden-netlist-that-allows-exceptions","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2022\/08\/29\/3d-ic-verification-requires-a-golden-netlist-that-allows-exceptions\/","title":{"rendered":"3D IC verification requires a golden netlist that allows exceptions"},"content":{"rendered":"\n

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers need to ensure that the system-level netlist is golden, i.e., it is the absolute reference of system connectivity. When running LVS-type verification between the 3D IC assembly layout and the 3D IC assembly system-level netlist, it is essential that any reported LVS error is related to the physical\/logical routing\u2014not the 3D IC netlist. Hence, a high level of confidence is expected in the connectivity information provided by the 3D IC system level netlist. <\/p>\n\n\n\n

Another challenge when verifying the connectivity of a multi-substrate 3D IC design is the project version-based connectivity exceptions, i.e., the need for creating shorts\/opens while physically implementing the substrates. Designers need to treat these opens\/shorts as \u201cexpected\u201d errors and differentiate them from the \u201creal\u201d and \u201cundesirable\u201d errors.<\/p>\n\n\n\n

In a recent white paper, Managing system level netlist challenges for 3D IC assemblies in advanced package designs<\/em><\/a>, we present a flow based on the Xpedition Substrate Integrator (xSI)<\/a> and Calibre 3DSTACK<\/a> tools that offers a fast, automated, and flexible \u201cnetlist versus netlist\u201d approach, so that you can be confident that the system-level connectivity captured in xSI is correct. Additionally, we show that xSI and Calibre 3DSTACK can support known shorts and opens so that connectivity exceptions can be handled seamlessly.<\/p>\n\n\n\n

Check out the paper<\/a> for some \u201cinsider\u201d info to begin confidently creating tomorrow\u2019s 3D IC designs today and get a head start on all the advantages this exciting technology can deliver for your company.<\/p>\n\n\n\n

Also have a look at my previous blog, 3D IC takes a village but must start with a netlist<\/a>, where I discuss a workflow that lets the package architect aggregate, construct, and manage a system-level gold netlist that drives all downstream design processes. <\/p>\n","protected":false},"excerpt":{"rendered":"

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…<\/p>\n","protected":false},"author":82986,"featured_media":93,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[374],"tags":[473,479],"industry":[103],"product":[142,368],"coauthors":[480],"class_list":["post-92","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ebook","tag-3d-ic","tag-netlist","industry-electronics-semiconductors","product-calibre","product-xpedition-ic-packaging"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2022\/08\/Calibre-design-solutions-is646054224-hero-2560x1440-1.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/92","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/users\/82986"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/comments?post=92"}],"version-history":[{"count":2,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/92\/revisions"}],"predecessor-version":[{"id":95,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/92\/revisions\/95"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media\/93"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media?parent=92"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/categories?post=92"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/tags?post=92"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/industry?post=92"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/product?post=92"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/coauthors?post=92"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}