{"id":825,"date":"2025-05-21T08:45:17","date_gmt":"2025-05-21T12:45:17","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=825&#038;preview=true&#038;preview_id=825"},"modified":"2026-03-27T09:12:16","modified_gmt":"2026-03-27T13:12:16","slug":"3d-ic-technology-trends-how-advanced-ic-packaging-is-changing-the-semiconductor-industry","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2025\/05\/21\/3d-ic-technology-trends-how-advanced-ic-packaging-is-changing-the-semiconductor-industry\/","title":{"rendered":"\u200b3D IC technology trends: how advanced IC packaging is changing the semiconductor industry"},"content":{"rendered":"\n<p>The semiconductor industry is rapidly evolving with 3D IC technology and advanced packaging solutions revolutionizing chip design and manufacturing. In this latest Siemens EDA podcast episode, we explore how these innovations are transforming the future of semiconductor integration. Join us as we welcome Jan Vardaman, President of TechSearch International, who shares expert insights on heterogeneous integration, chiplet ecosystems, and the emerging landscape of 3D ICs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Essential 3D IC technology insights from industry experts<\/strong>:&nbsp;<\/h2>\n\n\n\n<p>The adoption of 3D IC technology represents a paradigm shift in semiconductor design. As the industry moves beyond traditional scaling methods, advanced packaging and chiplet-based approaches are becoming crucial for next-generation electronics. This episode explores:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Market drivers accelerating 3D IC adoption<\/li>\n\n\n\n<li>Advanced packaging solutions enabling heterogeneous integration<\/li>\n\n\n\n<li>Emerging trends in chiplet design methodology<\/li>\n\n\n\n<li>AI&#8217;s role in modern semiconductor design<\/li>\n\n\n\n<li>Supply chain evolution in the 3D IC ecosystem<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Comprehensive guide to modern semiconductor integration<\/strong><\/h2>\n\n\n\n<p>Our in-depth discussion covers critical aspects of 3D IC technology implementation:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>[02:10] Advanced integration drivers<\/strong>:&nbsp;Explore the business and technical motivations driving the industry&#8217;s shift toward 3D IC adoption, including cost optimization and performance requirements.<\/li>\n\n\n\n<li><strong>[03:10] Market segment analysis<\/strong>:&nbsp;Discover which industries are leading the charge in chiplet design implementation and why these segments are particularly suited for advanced integration.<\/li>\n\n\n\n<li><strong>[06:50] Packaging requirements<\/strong>:&nbsp;Learn about the essential considerations and requirements for successful 3D IC integration, from thermal management to signal integrity.<\/li>\n\n\n\n<li><strong>[08:20] Substrate technologies:<\/strong>&nbsp;Deep dive into the comparative analysis of silicon, RDL, glass core, and organic interposer solutions for different applications.<\/li>\n\n\n\n<li><strong>[10:55] Siemens innovation<\/strong>:&nbsp;Get an exclusive overview of the Innovator3D IC platform and its role in advancing semiconductor design capabilities.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><strong><strong>Watch the full 3D IC technology discussion<\/strong><\/strong><\/h2>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"5 Game-changing 3D IC trends transforming semiconductors - Podcast Ep. 9\" width=\"640\" height=\"360\" src=\"https:\/\/www.youtube.com\/embed\/k-plEwattvk?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<p class=\"has-text-align-center\"><em>Bookmark our 3D IC podcast YouTube playlist for more insights on semiconductor innovation<\/em>!<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Complete episode transcript: 3D IC technology and advanced packaging solutions<\/strong><\/h2>\n\n\n\n<details>\n<summary><b>Click here to view the episode transcript<b><\/summary>\n\n<p> <p><b><strong>John McMillan (2.76)<\/strong><\/b>\n\n<p>From the drive towards miniaturization to the integration of complex\nfunctions through advanced packaging and 3D ICs, the future of IC technology is\nbeing reshaped before our very eyes. With the industry projected to reach a\nstaggering $1 trillion market by 2030, companies are faced with the challenge\nof accelerating innovation while managing the ever-increasing complexities of\n3D IC design and manufacturing. With that, let me welcome you to the 2025\nSiemens EDA Podcast Series on 3D IC Chiplet Ecosystems, brought to you by the\nSiemens Thought Leadership Team. I&#8217;m your host, John McMillan. This podcast\nseries dives into the exciting world of semiconductor chiplet integration and\nadvanced technology platforms using 2.5 and 3D IC techniques. I&#8217;ll be talking to\nindustry leaders and subject matter experts to discuss the latest 3D IC\nindustry trends and roadmaps and uncover how the semiconductor industry is\nworking diligently to make 3D IC mainstream.<\/p>\n\n<p>In today&#8217;s podcast, I am excited to be joined by my special guest, Jan\nVardaman, President of Tech Search International, to discuss the advanced\npackaging and heterogeneous integration roadmap for semiconductor scaling.\nWelcome, Jan, and thank you for taking the time to talk with me today. Before\nwe dive into the discussion, please tell our listeners a little about yourself,\nyour current role, and your background.<\/p>\n\n<p><strong>Jan Vardaman (1:21)<\/strong><\/p>\n\n<p>Well, our company is 37 years old, and we&#8217;ve been covering developments in\npackaging since before it became so popular. Our focus is entirely on advanced\npackaging, and the developments we&#8217;re seeing now are happening faster than\never. We&#8217;re very excited to discuss some of these topics with everyone.<\/p>\n\n<p><strong>John McMillan (1:50)<\/strong><\/p>\n\n<p>Great. So, as a company laser-focused on the semiconductor packaging market,\nwhat do you see as the main drivers for advanced integration heterogeneous or\nhomogeneous silicon from both a technology and business point of view?<\/p>\n\n<p><strong>Jan Vardaman (2:05)<\/strong><\/p>\n\n<p>Well, cost is always a major driver. The reason we&#8217;re seeing so much\ninterest in the idea of the chiplet is that it offers a new way to design an\nIC. We can no longer afford to fabricate everything as a monolithic die on the\nmost expensive nodes. That being said, it doesn t mean we won t continue with\nmonolithic die. If you can do it, you should. But there are many cases where\npart of the IC design doesn&#8217;t scale as well as the logic. So, why would you\nwant to fabricate a large portion of that die in a very expensive leading-edge\nnode, like a 5 or 3-nanometer node, when it could be fabricated in a legacy\nnode to save money on your silicon fab costs?<\/p>\n\n<p> It&#8217;s really about silicon fab cost and the idea of disaggregating the IC\ndesign, then putting it back together in the package to achieve the highest\nperformance possible. In many cases, you can also achieve a more\nenergy-efficient solution in terms of your picojoules per bit measurement.<\/p>\n\n<p><strong>John McMillan (3:35)<\/strong><\/p>\n\n<p>Gotcha. That&#8217;s really insightful. So, given this, are there any specific\nmarket segments and industries that are driving these activities? For example,\nwe hear a lot about hyperscale AI and HPC (high-performance compute), but is\nthat the whole picture, or is there a broader set of players and markets\ninvolved?<\/p>\n\n<p><strong>Jan Vardaman (3:57)<\/strong><\/p>\n\n<p>Well, there are other applications. Today, NVIDIA processors up until\nBlackwell were monolithic die designs packaged with HBM, which I&#8217;d consider a\nform of heterogeneous integration, where communication happens between the GPU\nand HBM. With the chiplet designs that have been implemented, you&#8217;ve seen many\ndesigns over the last several years from AMD for servers, desktops, and gaming.\nThe arguments they&#8217;ve made for chiplet designs are that the savings on the\nsilicon side make up for any additional cost for the package. It&#8217;s truly\nsignificant savings on the silicon side.<\/p>\n\n<p>They have the ability to do this architecture internally with their\ncapabilities. What many people want to see now is the ability to include\nthird-party chiplet designs into their own design. The industry is working on\nthis, but there are challenges especially around testing, communication between\nchiplets, and the protocols involved.<\/p>\n\n<p>It will be interesting to see how things develop. But we&#8217;re certainly in an\nera where we&#8217;re moving in that direction. For instance, NVIDIA&#8217;s new GPU for AI\nuses a chiplet architecture in a new package from TSMC called CoWoS-L, which is\nan RDL interposer. AMD&#8217;s MI300 series, currently in production, is a chiplet\ndesign, and interestingly, that design uses 3D stacking and hybrid bonding,\nachieving impressive energy efficiency alongside outstanding performance.<\/p>\n\n<p>So, we&#8217;re seeing a combination of both heterogeneous integration and chiplet\ndesign in the market. Each company has a different approach, depending on their\ninternal capabilities, design philosophy, and tools. So, we&#8217;ll see a variety of\ndifferent options moving forward.<\/p>\n\n<p><strong>John McMillan (6:49)<\/strong><\/p>\n\n<p>Yeah, gotcha. So clearly, there&#8217;s a much broader set of industry interests\nthan what we typically hear about. Some of these industries and markets are\ndifferent. Are they all looking for the same integration solution or platform,\nor do they have different needs that require different technologies or\nplatforms?<\/p>\n\n<p><strong>Jan Vardaman (7:08)<\/strong><\/p>\n\n<p>Well, I think you&#8217;re referring to the packaging solutions. Everyone has a\ndifferent approach depending on their particular supply chain and capabilities.\nFor example, the MI300 series uses a silicon interposer, a CoWoS done turnkey\nby TSMC.<\/p>\n\n<p><strong>John McMillan (7:11)<\/strong><\/p>\n\n<p>Yeah.<\/p>\n\n<p><strong>Jan Vardaman (7:32)<\/strong><\/p>\n\n<p>You also see the new Blackwell and Hopper series using the silicon\ninterposer, CoWoS. The new Blackwell uses CoWoS-L, as I mentioned, with an RDL\ninterposer instead of a silicon interposer. If you look at other solutions,\nAmazon uses CoWoS-R, which is the RDL solution without bridges. CoWoS-L, on the\nother hand, has silicon bridges.<\/p>\n\n<p>Intel prefers embedded bridge technology in the laminate substrate, which\nthey use for some of their server products and high-end applications. So,\nthere&#8217;s a variety of package options available. A chiplet is really the\narchitecture the way you design the IC and it&#8217;s put into the package you choose\nbased on your design philosophy and your supply chain.<\/p>\n\n<p><strong>John McMillan (8:42)<\/strong><\/p>\n\n<p>Gotcha. That makes it much clearer for me, and I hope for our listeners as\nwell. There&#8217;s been a lot published recently about substrate materials silicon,\nRDL, glass core, flexible glass, organic interposer bridges, etc. Are these all\ncompeting against each other, or do they have specific applications? And if so,\nhow should a design team choose one over the other?<\/p>\n\n<p><strong>Jan Vardaman (9:06)<\/strong><\/p>\n\n<p>Well, it all depends on what you&#8217;re trying to achieve. For example, using a\nsilicon interposer or an RDL interposer still requires a buildup substrate,\ntypically with a C4 bump. You have your die, interposer, and substrate. RDL\nstructures can either have an embedded silicon bridge or not. These solutions\nare favored by AMD and NVIDIA for high-performance cases.<\/p>\n\n<p>Intel has favored the EMIB solution, where the bridge is embedded in a\nlaminate substrate, achieving higher density where the bridge is located.\nThere&#8217;s been a lot of debate over which solution is the most cost-effective,\nbut again, it depends on your design and other factors, including your supply\nchain.<\/p>\n\n<p>A number of people are moving toward RDL interposers, as we believe this\nallows for pitch scaling to much higher densities than a laminate organic\nsubstrate. There&#8217;s also potential with silicon bridges, maybe with TSVs or\nother capabilities, allowing for finer pitch scaling. Ultimately, it&#8217;s about\nunderstanding your internal capabilities and what system-level performance you\nwant to achieve.<\/p>\n\n<p>At the end of the day, there&#8217;s no single packaging solution we can point to\nand say,  This is it,  because it depends on many different factors.<\/p>\n\n<p><strong>John McMillan (11:40)<\/strong><\/p>\n\n<p>Gotcha. Great conversation, Jan. Thanks for joining me today on the podcast\nand for sharing your knowledge on this exciting and fast-moving area of\ntechnology. Also, I&#8217;d like to take a moment to mention that Siemens Innovator\n3D IC platform was named the winner of the prestigious 3D InCites 2025 Award\nfor Technology Enablement.<\/p>\n\n<p><strong>Jan Vardaman (11:51)<\/strong><\/p>\n\n<p>Thanks so much.<\/p>\n\n<p><strong>John McMillan (12:04)<\/strong><\/p>\n\n<p>It was quite an honor. And if you&#8217;re not familiar with the Innovator 3D IC\nplatform, it s an AI-enhanced co-design tool that ensures digital continuity\nthrough system-centric planning for die, interposer, package, and PCB design.\nIt provides early insights into thermal, mechanical, and electrical\nperformance, reducing redesign iterations, and accelerating development.<\/p>\n\n<p>I hope you found this podcast educational and insightful. I certainly did,\nand I feel a lot more empowered now when I talk to designers about advanced\nsemiconductor packaging. We&#8217;re out of time for now, but thank you for joining\nus. Be sure to check out the show notes to learn more about 3D IC and the\nInnovator 3D IC platform. Don t forget to subscribe so you don t miss the next\nepisode of the 3D IC podcast.<\/p>\n <\/p>\n<\/details>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Connect with 3D IC technology leaders<\/strong><\/h2>\n\n\n\n<div class=\"wp-block-group is-vertical is-layout-flex wp-container-core-group-is-layout-8cf370e7 wp-block-group-is-layout-flex\">\n<p><strong>Connect with Jan Vardaman<\/strong>, President, TechSearch International &#8211; &nbsp;<a href=\"https:\/\/www.linkedin.com\/in\/e-jan-vardaman-425154a\/\" target=\"_blank\" rel=\"noreferrer noopener\">LinkedIn<\/a>&nbsp;<a href=\"https:\/\/www.techsearchinc.com\/\" target=\"_blank\" rel=\"noreferrer noopener\">Website<\/a>&nbsp;<\/p>\n\n\n\n<p><strong>Connect with John McMillan<\/strong>, Siemens EDA &#8211;&nbsp;<a href=\"https:\/\/www.linkedin.com\/in\/johnmcmillan\/\" target=\"_blank\" rel=\"noreferrer noopener\">LinkedIn<\/a>&nbsp;<\/p>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Explore more 3D IC innovation content<\/strong><\/h2>\n\n\n\n<p>Stay informed about the latest developments in 3D IC technology:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Bookmark the <a href=\"https:\/\/www.youtube.com\/playlist?list=PL1m1vu8_quoAcV1ryR_0Q1gSLf6_VWY6e\" target=\"_blank\" rel=\"noopener\">3D IC podcast playlist<\/a><\/li>\n\n\n\n<li>Visit the <a href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/3d-ic-design\/\" target=\"_blank\" rel=\"noopener\">3D IC design and packaging solutions page <\/a><\/li>\n\n\n\n<li>Access our <a href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/3d-ic-design\/3d-ic-resources\/\" target=\"_blank\" rel=\"noopener\">3D IC technical resource library<\/a><\/li>\n\n\n\n<li>Explore <a href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/innovator3d-ic\/\" target=\"_blank\" rel=\"noopener\">Innovator3D IC<\/a>, the unified cockpit for design planning!<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Siemens 3D IC design solution<\/strong><\/h2>\n\n\n\n<p>Transform your semiconductor design approach with our comprehensive 3D IC design flow, featuring:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Heterogeneous 2.5\/3D integration<\/strong><\/li>\n\n\n\n<li><strong>3D SoIC implementation<\/strong><\/li>\n\n\n\n<li><strong>Substrate implementation<\/strong><\/li>\n\n\n\n<li><strong>Functional verification<\/strong><\/li>\n\n\n\n<li><strong>Electrical simulation &amp; sign-off<\/strong><\/li>\n\n\n\n<li><strong>Mechanical co-design<\/strong><\/li>\n\n\n\n<li><strong>Physical verification<\/strong><\/li>\n\n\n\n<li><strong>Thermal\/mechanical simulation<\/strong><\/li>\n\n\n\n<li><strong>Product lifecycle management<\/strong><\/li>\n\n\n\n<li><strong>2.5D\/3D design-for-test<\/strong><\/li>\n\n\n\n<li><strong>Verification IP for 3D IC<\/strong><\/li>\n\n\n\n<li><strong>3D IC design &amp; verification<\/strong><\/li>\n\n\n\n<li><strong>Design for reliability<\/strong><\/li>\n<\/ul>\n\n\n\n<p><strong>Ready to improve your IC design process?<\/strong>&nbsp;<a href=\"https:\/\/www.siemens.com\/3dic\/?ref=EBS_blog\" target=\"_blank\" rel=\"noopener\">Learn More About Siemens 3D IC Solutions<\/a> \u2192<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The semiconductor industry is rapidly evolving with 3D IC technology and advanced packaging solutions revolutionizing chip design and manufacturing. In&#8230;<\/p>\n","protected":false},"author":71824,"featured_media":897,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[378],"tags":[473,548,475,477,474,471,549],"industry":[103,106],"product":[535,368],"coauthors":[509],"class_list":["post-825","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-podcast","tag-3d-ic","tag-advanced-packaging","tag-chiplet","tag-heterogeneous-design","tag-integrated-circuit","tag-semiconductors","tag-siemens-eda","industry-electronics-semiconductors","industry-semiconductor-devices","product-innovator3d-ic","product-xpedition-ic-packaging"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2025\/04\/3D-IC-Podcast-1-Featured-1200x627-1.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/825","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/users\/71824"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/comments?post=825"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/825\/revisions"}],"predecessor-version":[{"id":967,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/825\/revisions\/967"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media\/897"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media?parent=825"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/categories?post=825"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/tags?post=825"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/industry?post=825"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/product?post=825"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/coauthors?post=825"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}