{"id":565,"date":"2024-07-31T07:32:04","date_gmt":"2024-07-31T11:32:04","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=565"},"modified":"2026-03-27T09:11:37","modified_gmt":"2026-03-27T13:11:37","slug":"siemens-introduces-innovator3d-ic-a-comprehensive-multiphysics-cockpit-for-3d-ic-design-verification-and-manufacturing","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2024\/07\/31\/siemens-introduces-innovator3d-ic-a-comprehensive-multiphysics-cockpit-for-3d-ic-design-verification-and-manufacturing\/","title":{"rendered":"Siemens introduces Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing"},"content":{"rendered":"\n

During the Design Automation Conference (DAC) 2024 in San Francisco – AJ Incorvaia, Senior Vice President responsible for the Electronic Board Systems Group within Siemens EDA announced Innovator3D IC, new software that delivers a fast, predictable path for the planning and heterogeneous integration of ASICs and chiplets using the latest and most advanced semiconductor packaging 2.5D & 3D technologies and substrates in the world.<\/p>\n\n\n\n

Click here<\/a> to watch the Innovator3D IC keynote presentation video (6-minutes)<\/p>\n\n\n\n

Innovator3D IC provides a consolidated cockpit for constructing a digital twin — featuring a unified data model for design planning, prototyping and predictive analysis — of the complete semiconductor package assembly. This cockpit drives implementation, multi-physics analysis, mechanical design, test, signoff, and release to manufacturing.<\/p>\n\n\n\n

By unifying power, signal, thermal, and mechanical stress analysis tools, it enables rapid \u2018what-if\u2019 exploration, while identifying, avoiding and solving challenges prior to detailed design implementation. This shift-left approach can prevent costly and time-consuming downstream rework or suboptimal results.<\/p>\n\n\n\n

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Siemens already had the most comprehensive portfolio of semiconductor packaging related technologies available as part of Siemens Xcelerator, by combining these with Innovator3D IC we enable customers to achieve the realization of more-than-Moore.\u201d<\/em><\/p>\nAJ Incorvaia, Sr. VP of Electronic Board Systems at Siemens Digital Industries Software<\/em><\/cite><\/blockquote>\n\n\n\n

Innovator3D IC provides a unified cockpit<\/strong><\/h2>\n\n\n\n

Innovator3D ICs unified cockpit is <\/strong>for design planning, prototyping and predictive multi-physics analysis. This cockpit constructs a power, performance, and area (PPA) and cost optimized digital twin of the complete semiconductor package assembly that in turn drives implementation, multi-physics analysis, mechanical design, test, signoff, and release to fabrication and manufacturing through a managed and secure design IP digital thread conduit<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Innovator3D IC open architecture built around STCO<\/strong><\/h2>\n\n\n\n

Innovator3D IC is architected around the system technology co-optimization (STCO) methodology process developed by IMEC. STCO is utilized throughout prototyping and planning, design, sign-off, and manufacturing hand-off, concluding with comprehensive verification and reliability assessment. Although the Innovator3D IC cockpit is directly integrated with the extensive Siemens Xcelerator technology portfolio, it supports the integration of third-party point solutions, recognizing that customers may have incumbent third party tools in their current design flows that they wish to continue using.<\/p>\n\n\n\n

Single digital twin data model of entire assembly<\/strong><\/h2>\n\n\n\n

Innovator3D IC constructs and maintains a 3D digital twin of the entire device including chiplets, interposers, substrates, and even the system PCB. Through its hierarchical device planning capability, chiplet and ASIC floorplans and their external interface assignments can be defined and optimized for overall PPA and cost targets. A hierarchical ECO flow with PANDR implementation tools allows for localized optimization of the individual chiplet, ASIC, interposer, package PPA and timing as well as with the overall device.<\/p>\n\n\n\n

Industry standards support<\/strong><\/h2>\n\n\n\n

A key tenant of Innovator3D IC is the support of industry standard formats, protocols, and API interfaces. The first key area is the commitment and support for the 3Dblox\u2122 standard that enables EDA tool interoperability, bringing the benefits of improved productivity and efficiency to end users and customers in 3D IC system level designs. The next is to ensure frictionless adoption and consumption of existing and new die-to-die inter[1]face IP, such as UCIe and BoW. The Open Compute Projects Chiplet Design Exchange Working Group (OCP CDX) has enabled direct consumption of standardized chiplet models that will be provided by the emerging commercial chiplet ecosystem<\/p>\n\n\n\n

Hierarchical device planning<\/strong><\/h2>\n\n\n\n

Advanced 2.5\/3D heterogeneously integrated designs containing multiple chiplets commonly have pin counts in the hundreds of millions. Designers face a major bottleneck in design assembly and ECO updates with such designs. Using only a top-level synthesis approach causes gaps for most practical applications, while taking analysis to the bump level everywhere is very time and resource consuming. Innovator3D IC uses a hierarchical device planning approach, which represents designs as geometrically partitioned (smart pin) regions with para[1]metric attributes. These attributes indicate how each region should be elaborated, using hierarchical reuse, and physically implemented, using known good layout techniques. Designers can thus quickly implement critical updates while matching analytic methods to specific smart pin regions to avoid extremely high execution times.<\/p>\n\n\n\n

Chiplet to chiplet interface planning<\/strong><\/h2>\n\n\n\n

Inter-chiplet communications are crucial to deliver the performance and bandwidth needed by high-performance computing and AI devices while meeting power requirements. Hierarchical interface route path sketch planning allows designers to explore interface route path channels and optimize chiplet interface and pin assignments. The results are passed to detailed place-and-route for PDK correct implementation.<\/p>\n\n\n\n

Predictive multiphysics analysis<\/strong><\/h2>\n\n\n\n

During prototyping and planning it is critical to evaluate the performance of all design scenarios before committing the design to implementation. Innovator3D IC integrates directly with power, signal, thermal, and mechanical stress analyses so that a design scenario can be evaluated quickly and any issues explored and resolved prior to detailed design implementation. This shift-left approach prevents costly and time-consuming downstream rework or sub-optimal results<\/p>\n\n\n\n

Comprehensive workflow support<\/strong><\/h2>\n\n\n\n

Once a system\u2019s architecture has been partitioned or decomposed into its various implementation targets\u00a0 \u2014 such as chiplets, 3DSoC, ASICs, and memory\u00a0\u2014 Innovator3D IC drives a set of comprehensive workflows, using a dynamically managed digital thread data model of the assembly\u2019s digital twin.<\/p>\n\n\n\n

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For advanced heterogeneous integration platforms such as EMIB, an integrated floorplanning and prototyping cockpit with predictive analysis is essential – through our collaboration with Siemens EDA, we see Innovator3D IC as an important design technology component for our advanced integration platforms.\u201d<\/em><\/p>\nSuk Lee, VP & GM of Ecosystem Technology Office, at Intel Foundry.<\/cite><\/blockquote>\n\n\n\n

Built on next generation electronic systems design<\/strong><\/h2>\n\n\n\n

Innovator3D IC is built on the same architecture as our next generation electronic systems design. This architecture delivers new capabilities in five key ways:<\/p>\n\n\n\n

    \n
  1. Intuitive<\/li>\n\n\n\n
  2. AI-infused<\/li>\n\n\n\n
  3. Ecosystem connected<\/li>\n\n\n\n
  4. Integrated<\/li>\n\n\n\n
  5. Secure<\/li>\n<\/ol>\n\n\n\n

    Innovator3D IC drives ASIC, chiplet and Interposer implementation using Siemens’ Aprisa\u2122 software digital IC place and route technology, Xpedition\u2122 Package Designer software, Calibre\u00ae 3DThermal software, NX\u2122 software for mechanical design, Tessent\u2122 Test software, and Calibre\u00ae 3DSTACK software for interchiplet DRC, LVS and tapeout signoff.<\/p>\n\n\n\n

    Learn more about Inovator3D IC<\/h2>\n\n\n\n

    Innovator3D IC is expected to be available later in 2024. To learn more about Siemens\u2019 Innovator3D IC software Click here<\/a><\/p>\n\n\n\n

    Download the Innovator3D IC brochure: Click here<\/a><\/p>\n\n\n\n

    Read the press release Click here<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

    Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing<\/p>\n","protected":false},"author":71824,"featured_media":568,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[376,1],"tags":[473,482,533,471,534],"industry":[103,106],"product":[535,368],"coauthors":[509],"class_list":["post-565","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-featured","category-news","tag-3d-ic","tag-ic-packaging","tag-innovator3d-ic","tag-semiconductors","tag-xcelerator","industry-electronics-semiconductors","industry-semiconductor-devices","product-innovator3d-ic","product-xpedition-ic-packaging"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2024\/07\/siemens-innovator3d-ic-newsroom-01-1280x720-1.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/565","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/users\/71824"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/comments?post=565"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/565\/revisions"}],"predecessor-version":[{"id":573,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/565\/revisions\/573"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media\/568"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media?parent=565"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/categories?post=565"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/tags?post=565"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/industry?post=565"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/product?post=565"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/coauthors?post=565"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}