![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2022\/07\/Semiconductor_trends_1200x900_3-1024x768.jpg\")
<\/figure><\/div>\n\n\nProblems with large areas of metal fill in manufacturing<\/strong>\u00a0<\/h2>\n\n\n\nWhen you create large areas of metal, you can also create manufacturing issues. The first and most obvious is around the actual successful creation that meets the manufacturer\u2019s often stringent criteria. Then there is substrate warpage, where uneven conductor densities on the same layer or across layer pairs can cause warpage and another around outgassing or offgassing. During the substrate build-up and RDL manufacturing process the dielectric and metal layers can suffer from areas of delamination due to trapped pockets of gas caused by materials using in substrate manufacturing containing salts or organics that create the gas during the fabrication process. <\/p>\n\n\n\n
This obviously impacts the production yield of the substrate, as well as the reliability and lifecycle of the device. Think of it being like adding a screen protector to your smartphone and how hard it is to get the air bubbles out. So as a result, substrate fabricators and manufacturers do not like solid metal planes or large metal areas. To avoid such issues, they typically provide designers with strict metal fill requirements in the form of rules, design rule checks, and often a design rule manual (DRM). <\/p>\n\n\n\n
As you can imagine the combination of these issues and all the rules makes the designer\u2019s job of meeting the fabricators acceptance criteria a challenge. Further, the diversity of substrate technologies from numerous vendors means there\u2019s no one-size-fits-all solution.\u00a0\u00a0\u00a0<\/p>\n\n\n\n
Methods to control metal fill issues<\/strong>\u00a0<\/h2>\n\n\n\nHowever, there are three methodologies that are typically used by designers to mitigate\/control issues. The first is hatched filled metal areas with layer offsets. The second is the insertion of outgassing void patterns and the third is the addition\/insertion of dummy metal fill. <\/p>\n\n\n\n
These are the most common methods to achieve the substrate fabricators requirements for metal areas and planes in advanced package designs such as interposers, high-density-fan-out wafer level package (HDFOWLP), and high pin count flip chip BGAs, so it is important to understand how to use them efficiently and effectively in order to prevent extended design cycles or ECO\u2019s due to fabricator rejection of the design. <\/p>\n\n\n\n
However, there are three methodologies that are typically used by designers to mitigate\/control issues. The first is hatched filled metal areas with layer offsets. The second is the insertion of outgassing void patterns and the third is the addition\/insertion of dummy metal fill. <\/p>\n\n\n\n
These are the most common methods to achieve the substrate fabricators requirements for metal areas and planes in advanced package designs such as interposers, high-density-fan-out wafer level package (HDFOWLP), and high pin count flip chip BGAs, so it is important to understand how to use them efficiently and effectively in order to prevent extended design cycles or ECO\u2019s due to fabricator rejection of the design. <\/p>\n\n\n\n