Historically, integrated circuit (IC) package design was straightforward, involving die bumps fanned out for connection to a printed circuit board. The package netlist was manually created by package designers using tools like Excel. However, modern package and interposer design is now a complex, system integration task. Designers must consider input from various stakeholders who may be concurrently designing content.<\/p>\n\n\n\n
The term \u201csubstrate\u201d generically represents both package and interposer designs. Despite differences in manufacturing technology and tools, the design and verification tasks remain similar. In both cases, rapid advances in package technology and the explosion of AI and high-performance computing applications give rise to design challenges that are breaking the existing methodologies used by substrate designers. These include:<\/p>\n\n\n\n
The appeal of functional verification is that it validates correct system connectivity and functionality and appears solvable due to in-house chip design. However, additional information is required beyond the main silicon device, such as:<\/p>\n\n\n\n
Challenges with Chiplets<\/strong><\/p>\n\n\n\n Chiplets, such as those for high-bandwidth memory (HBM), frequently lack functional models. Substrate designers face challenges due to limited access to chip RTL and verification environments, while expertise is required to adopt and execute verification tools.<\/p>\n\n\n\n Skillset Gap<\/strong><\/p>\n\n\n\n Developing specialized Verilog models and testbenches is not typically within the domain of package and interposer designers.<\/p>\n\n\n\n Practicality<\/strong><\/p>\n\n\n\n Technically possible but often impractical due to resource constraints.<\/p>\n\n\n\n LVS checks whether the physical implementation (layout) corresponds to the original schematic or circuit diagram of the design. It ensures that the devices and nets in the layout match those in the schematic. However, LVS alone doesn\u2019t guarantee functional correctness. It focuses on netlist consistency but does not assess functionality.<\/p>\n\n\n\n If the layout matches the source netlist, LVS considers the comparison \u201cclean.\u201d However, this approach assumes that the source netlist is accurate. If the source netlist contains errors or is incomplete, LVS may still \u201cpass\u201d even if the design is functionally flawed. The layout may match an incorrect netlist in such cases, leading to a false sense of security.<\/p>\n\n\n\n In short, LVS can identify physical discrepancies (e.g., shorts, opens) between the layout and schematic. But it cannot determine if the design functions correctly, assess whether the design performs its intended function, nor address questions related to design correctness. Designers must consider additional verification methods beyond LVS to ensure overall correctness.<\/p>\n\n\n\n Formal verification tools are suitable for verifying package connections early in the design process. These tools focus on connectivity checks without requiring extensive testbenches or assertions. And unlike simulation-based approaches, formal connectivity solutions don\u2019t necessitate understanding the design\u2019s functionality.<\/p>\n\n\n\n The benefits and considerations related to formal verification for verifying package connections in chiplets include:<\/p>\n\n\n\n As a bonus, when verifying package connections after prototyping, companies can use existing CSV specs or create new ones. The system top module and black boxes of the dies serve as the golden reference model for verification.<\/p>\n\n\n\n To learn more about modern package and interposer design, download this white paper entitled: “New innovative way to functionally verify heterogeneous 2D\/3D package connectivity.<\/em>“<\/strong><\/p>\n\n\n\nWhat About LVS? (layout versus schematic)<\/strong><\/h2>\n\n\n\n
Automatic Formal-Based Approach<\/strong><\/h2>\n\n\n\n
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Get the white paper<\/strong><\/h2>\n\n\n\n