{"id":330,"date":"2023-12-08T08:34:36","date_gmt":"2023-12-08T13:34:36","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=330"},"modified":"2026-03-27T09:11:01","modified_gmt":"2026-03-27T13:11:01","slug":"crossing-the-chasm-bringing-soc-and-package-verification-together","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2023\/12\/08\/crossing-the-chasm-bringing-soc-and-package-verification-together\/","title":{"rendered":"Crossing the chasm: Bringing SoC and package verification together"},"content":{"rendered":"\n

Accurate verification of fan-out wafer-level packaging (FOWLP) designs requires the integration of package design environments with system-on-chip (SoC) verification tools to ensure package manufacturability and performance.<\/p>\n\n\n\n

Wafer-level packaging (WLP) certainly enables higher form factor and improved performance compared to traditional SoC designs – however, to achieve acceptable yield and performance – electronic design automation (EDA) companies, outsourced assembly and test (OSAT) companies, and foundries must collaborate to establish consistent, unified, and automated die-level signoff verification to 2.5D and 3D stacked die assemblies. This includes fan-out wafer-level packaging (FOWLP), to ensure manufacturability and performance – while introducing minimum disruption to existing package design flows.<\/p>\n\n\n\n

Wafer-level packaging<\/h2>\n\n\n\n

WLP is a promising \u201cMore than Moore\u201d technology that enables higher form factor and improved performance compared to traditional SoC designs. Unlike 2.5D and 3D integrated circuit (IC) designs, WLP doesn\u2019t require through-silicon vias (TSVs), which are expensive and may cause mechanical and thermal reliability issues.<\/p>\n\n\n\n

There are two WLP styles predominantly in use: fan-in and fan-out. Both of these styles enable single-die and multi-die integration. However, for the multi-die fan-in process, multiple dies are typically from the same silicon wafer (homogenous integration). In the case of FOWLP, the die integration can be either homogenous or heterogeneous. FOWLP design for example utilizes the package-level redistribution layers (RDLs) to connect from the die to external ball grid arrays (BGAs), and between die in multi-die configurations.<\/p>\n\n\n\n

FOWLP design and verification<\/h2>\n\n\n\n

From an IC packaging perspective, package design and verification flows are much simpler than those used for SoCs. However, for packaging technologies such as FOWLP the package design and verification process has become much more complicated. Because FOWLP manufacturing occurs at the \u201cwafer level,\u201d it incorporates mask generation, similar to the SoC manufacturing flow. That means solid package design and verification flows must be in place so the designer can ensure the manufacturability of the FOWLP by the foundry or OSAT company. Similar to the PDKs used for an SoC, the foundry or OSAT must now provide the package designer with some form of an assembly design kit (ADK), as shown in Figure 1.<\/p>\n\n\n

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Figure 1 Package ADK components<\/p>\n\n\n\n

Addressing the challenges that uniting ICs and packages presents requires new EDA functionality that bridges the gap between the IC world and the packaging world while introducing minimal disruption to the already-existing package design flows. This new design platform must also contain several verification tools that can be used for FOWLP designs that:<\/p>\n\n\n\n