{"id":1354,"date":"2026-04-27T08:00:00","date_gmt":"2026-04-27T12:00:00","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=1354"},"modified":"2026-05-06T09:28:58","modified_gmt":"2026-05-06T13:28:58","slug":"whats-new-in-innovator3d-ic-2604","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2026\/04\/27\/whats-new-in-innovator3d-ic-2604\/","title":{"rendered":"What&#8217;s new in Innovator3D IC 2604"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">Streamlining 3D IC Design with Innovator3D IC 2604<\/h2>\n\n\n\n<p>This&nbsp;latest Innovator3D IC release brings a&nbsp;raft of design capability and productivity enhancements&nbsp;to the product family, further enabling its ability to&nbsp;design for&nbsp;the latest&nbsp;AI and&nbsp;Hyperscaler&nbsp;devices using advanced heterogeneous integration platforms.&nbsp;One major area of focus for 2604 was introducing AI to power a number of&nbsp;complex&nbsp;functions&nbsp;that without AI would be very time consuming and error prone.&nbsp;Those capabilities are covered in&nbsp;greater detail in&nbsp;another <a href=\"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2026\/04\/27\/streamlining-ai-device-design-using-ai-and-innovator3d-ic-integrator\/\">blog post<\/a>.&nbsp;Here&nbsp;is a preview of the&nbsp;non-AI&nbsp;major new capabilities.&nbsp;<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Innovator3D IC Integrator<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>System netlist comparator&nbsp;with graphical debugger&nbsp;\n<ul class=\"wp-block-list\">\n<li>Early pathfinding&nbsp;SVS (Schematic-Verses-Schematic) comparison&nbsp;can prevent later stage detailed LVS\/assembly issues causing a design spin.&nbsp;<\/li>\n\n\n\n<li>A graphical&nbsp;comparator provides&nbsp;checking\/debugging allowing designers to quickly pinpoint issues such as&nbsp;missing pins, superfluous pins, superfluous pins on&nbsp;a&nbsp;foreign&nbsp;net&nbsp;as&nbsp;well as pins connected to the wrong net.&nbsp;<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Comprehensive 3Dblox support&nbsp;\n<ul class=\"wp-block-list\">\n<li>Support for all&nbsp;revisions\/versions&nbsp;of 3Dblox.&nbsp;<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Expanded early predictive analysis capabilities&nbsp;for silicon&nbsp;substrates&nbsp;with resistivity calculation&nbsp;of the&nbsp;planned on&nbsp;silicon interconnect&nbsp;<\/li>\n\n\n\n<li>New unravel\/connectivity optimizer&nbsp;across devices&nbsp;and substrates&nbsp;<\/li>\n\n\n\n<li>Net length reporting and&nbsp;netline&nbsp;crossing congestion visualization and reporting&nbsp;\n<ul class=\"wp-block-list\">\n<li>Assist\u2019s&nbsp;designer in better route channel planning.&nbsp;<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Centralized property manager&nbsp;provides consistent use&nbsp;model&nbsp;for adding properties to objects&nbsp;used in&nbsp;early predictive analysis and&nbsp;downstream&nbsp;processes.&nbsp;<\/li>\n\n\n\n<li>Internal ASIC\/chiplet connectivity now used for daisy-chain test vehicle design&nbsp;<\/li>\n\n\n\n<li>New high-performance multi-threaded virtual die model&nbsp;provides interactive performance on design of 5M+ pin designs&nbsp;<\/li>\n\n\n\n<li>Direct import of&nbsp;Calibre&nbsp;verification results&nbsp;provides a streamlined debugging flow.&nbsp;&nbsp;<\/li>\n\n\n\n<li>Export to&nbsp;Tessent&nbsp;Diagnosis&nbsp;for early yield failure prediction&nbsp;<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Innovator3D IC Layout<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>New ultra-fast GDSII export engine&nbsp;&nbsp;<\/li>\n\n\n\n<li>Interactive, batch and forward annotation performance tested on 24 million pin design with 2 million nets&nbsp;&nbsp;<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Innovator3D IC Protocol Analyzer<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Advanced Solver material mapping\/management\u202f&nbsp;\n<ul class=\"wp-block-list\">\n<li>Integration with&nbsp;Calibre\u202fthat&nbsp;recreates&nbsp;nets, pins, embedded materials, etc. from shape properties.\u202f&nbsp;<\/li>\n\n\n\n<li>Calibre\u202fenhancements\u202finclude\u202fMIPT to .tech file translator enabling in-die table support.\u202f&nbsp;<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Innovator3D IC Data Management<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Tighter design integration\u202f&nbsp;\n<ul class=\"wp-block-list\">\n<li>Ability to check in local designs.\u202fDesign meta-data directly visible through Innovator3D IC Data Management\u202fcockpit, no need to open design to view meta data.\u202fImport all packaging design source data\/IP directly.\u202f&nbsp;<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<p>As you can see 2604 is rich is new capabilities that boost design capability and productivity.<\/p>\n\n\n\n<div class=\"wp-block-buttons is-layout-flex wp-block-buttons-is-layout-flex\">\n<div class=\"wp-block-button\"><a class=\"wp-block-button__link wp-element-button\" href=\"https:\/\/resources.sw.siemens.com\/en-US\/fact-sheet-innovator3d-ic-product-family-release-2604\/\" target=\"_blank\" rel=\"noopener\">Download fact sheet<\/a><\/div>\n<\/div>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This\u00a0latest Innovator3D IC release brings a\u00a0raft of design capability and productivity enhancements\u00a0to the product family, further enabling its ability to\u00a0design for\u00a0the latest\u00a0AI and\u00a0Hyperscaler\u00a0devices using advanced heterogeneous integration platforms.<\/p>\n","protected":false},"author":71666,"featured_media":1386,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[379],"tags":[477,482,533],"industry":[],"product":[535,368],"coauthors":[476],"class_list":["post-1354","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-product-updates","tag-heterogeneous-design","tag-ic-packaging","tag-innovator3d-ic","product-innovator3d-ic","product-xpedition-ic-packaging"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2026\/04\/whats-new_2604_1280x720_Innovator3DIC.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1354","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/users\/71666"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/comments?post=1354"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1354\/revisions"}],"predecessor-version":[{"id":1405,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1354\/revisions\/1405"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media\/1386"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media?parent=1354"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/categories?post=1354"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/tags?post=1354"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/industry?post=1354"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/product?post=1354"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/coauthors?post=1354"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}