The heterogeneous integration of multiple\u00a0chiplets\u00a0in a single packaging platform\u00a0is critical for\u00a0many\u00a0high-performance\u00a0compute\u00a0segments\u00a0such as AI,\u00a0Hyperscalers,\u00a0HPC,\u00a0Cloud datacenters,\u00a0neural\u00a0processors\u00a0and even autonomous vehicles.\u00a0With the\u00a0quantity of\u00a0chiplets\u00a0commonly exceeding\u00a0double-digit\u00a0numbers. Add to that the\u00a0increasing\u00a0usage of high-speed, low power and low latency high-bandwidth-memory\u00a0(HBM) stacks\u00a0the\u00a0resultant\u00a0designs\u00a0often exceed 1M+ total pins. With that many\u00a0device\u00a0pins\u00a0the\u00a0resultant\u00a0connectivity\u00a0is\u00a0massive\u00a0making the task\u00a0of verifying the connectivity\u2019s correctness exceptionally\u00a0challenging and\u00a0time consuming. <\/p>\n\n\n\n
The traditional way to verify the connections requires a lot of\u00a0manpower\u00a0and time and is either not exhaustive or too late in the process.\u00a0In this blog we\u00a0will introduce a new way to verify the package connectivity using formal verification that can exhaustively verify all interconnections between the\u00a0chiplet\u00a0blocks. The flow is automatic for all steps from creating\u00a0the\u00a0connectivity specification\u00a0to verifying the\u00a0package\u00a0assemblies\u00a0output connectivity. The automatic parallel algorithms\u00a0execute\u00a0on\u00a0a\u00a0compute\u00a0grid\u00a0and\u00a0verify\u00a0huge numbers\u00a0of connections in\u00a0minutes\u00a0even seconds. The script for\u00a0executing the\u00a0flow is simple and only takes a few minutes to setup. Once the script is ready, it can be reused for different package projects.\u00a0<\/p>\n\n\n\n
Historically\u00a0semiconductor\u00a0package design has been a\u00a0relatively simple\u00a0task\u00a0as it\u00a0involved\u00a0a single IC\/die\u00a0with\u00a0a\u00a0relatively\u00a0low number\u00a0of external bumps\u00a0(100\u2019s).\u00a0The\u00a0IC\/die bumps\u00a0are\u00a0fanout connected to the package ball-grid-array (BGA)\u00a0geometry suitable for connecting to a printed circuit board.\u00a0\u00a0The package netlist\u00a0connecting the IC\/die bumps to BGA\u00a0was often captured by the package\u00a0designer,\u00a0typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection.\u00a0<\/p>\n\n\n\n
Today\u2019s multi IC\/chiplet heterogeneously integrated packages often include interposers and is now a system integration task: The designer has the responsibility to take input from various stakeholders, who are often designing their content at the same time the package and\/or interposer is being designed and create a design which is both electrically and physically correct, but functions as designed too. <\/p>\n\n\n\n
Heterogeneous integration has brought with it some challenges for the package designer. The source data is being supplied in a myriad of data formats such as Ball map CSV files, LEF\/DEF from IC place and route tools, GDSII\/OASIS, Verilog RTL, spreadsheet\/csv data and of course plain text files. <\/p>\n\n\n\n
As each component of the design is introduced, it must be connected to the other components in the system. Spreadsheet based design requires every connection be defined as a scalar. High Bandwidth Memory (HBM) based designs with their 1024 bit width would be extremely tedious and error prone defining the connectivity one bit at a time. <\/p>\n\n\n\n
To handle the explosion of die-to-die connections, designers are embracing\u00a0language-based\u00a0design\u00a0to define the connectivity of the system.\u00a0\u00a0It is far more efficient and less error prone to write Verilog RTL using proper bus notation to connect the various components of a system together than it is to define the connectivity one bit at a time in a spreadsheet or develop specialized Excel macros to populate a connectivity table.\u00a0\u00a0Spreadsheet based solutions, even with custom macro development, do not scale\u00a0for\u00a0hundreds of thousands or millions of bumps. Through the use\u00a0of Siemens Innovator3D IC\u00a0Integrator\u00a0the\u00a0challenge of source data\u00a0aggregation\/integration\u00a0is quickly overcome,\u00a0creating a 3D Digital Twin model of the entire design.\u00a0The design connectivity can then be exported\u00a0for\u00a0verification,\u00a0this aggregated netlist can then be\u00a0validated\u00a0against the\u00a0reference netlist the design was assembled from by using a\u00a0functional\u00a0verification\u00a0process\u00a0and technology.\u00a0<\/p>\n\n\n\n