{"id":1277,"date":"2026-01-13T09:39:16","date_gmt":"2026-01-13T14:39:16","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/?p=1277"},"modified":"2026-03-27T09:13:11","modified_gmt":"2026-03-27T13:13:11","slug":"what-is-3dblox","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/2026\/01\/13\/what-is-3dblox\/","title":{"rendered":"What is 3Dblox?"},"content":{"rendered":"\n<p>If you have not heard of it before, 3Dblox is an emerging standard that was first created by TSMC but is&nbsp;now&nbsp;managed by IEEE who are in the process of turning it into open standard.&nbsp;It already has broad EDA,&nbsp;foundry&nbsp;and OSAT support and is being&nbsp;leveraged&nbsp;today across the ecosystem.&nbsp;<\/p>\n\n\n\n<p>What is its goal?&nbsp;<\/p>\n\n\n\n<p>As an open ecosystem cross collaboration format that will enable transparent collaboration between EDA tools.<\/p>\n\n\n\n<p><em>3Dblox, a hardware description language, serves the procompetitive purpose of modularizing and streamlining the 3D\u00a0IC package solutions available in the semiconductor industry, helping to enhance interoperability and unleash innovation for 3D\u00a0IC designs. 3Dblox is also aimed at improving the current error-prone 3D\u00a0IC design process, and saving time and cost by enabling different EDA tools to speak the same language and support\u00a0chiplet\u00a0design reuse features<\/em>.<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>Provides a uniform generic format that can be used by all EDA tools to describe the key physical stacking and the logical connectivity information in 3D\u00a0IC designs, making tool interoperability across any supported tools, as well as integrating data from multiple parties into a comprehensive 3D\u00a0IC design, a breeze.\u00a0<\/li>\n<\/ol>\n\n\n\n<ol start=\"2\" class=\"wp-block-list\">\n<li>Modularize 3D\u00a0IC structures to simplify the 3D\u00a0IC design flow and enable EDA tools to be more efficient and user-friendly\u00a0<\/li>\n<\/ol>\n\n\n\n<p>Siemens EDA&nbsp;is&nbsp;an early adopter of 3Dblox and our Innovator3D IC Integrator technology, which is a 2.5\/3D IC prototyping and pathfinding solution,&nbsp;can read, author, edit and write 3Dblox format across all three design abstraction levels.&nbsp;&nbsp;<\/p>\n\n\n\n<p>You can find\u00a0out\u00a0more on Innovator3D IC Integrator here:\u00a0<a href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/innovator3d-ic\/\" target=\"_blank\" rel=\"noreferrer noopener\">Innovator3D IC solution suite | Siemens Software<\/a>\u00a0<\/p>\n\n\n\n<p>What are&nbsp;3Dblox&nbsp;abstraction levels?&nbsp;The abstraction level is how devices, such as ASICs or&nbsp;Chiplets&nbsp;are described\/defined.&nbsp;<\/p>\n\n\n\n<ol start=\"1\" class=\"wp-block-list\">\n<li>Devices\u00a0can be\u00a0defined as a black box\u00a0<\/li>\n<\/ol>\n\n\n\n<ol start=\"2\" class=\"wp-block-list\">\n<li>Devices\u00a0can be\u00a0defined as LEF\/DEF\u00a0<\/li>\n<\/ol>\n\n\n\n<ol start=\"3\" class=\"wp-block-list\">\n<li>Devices\u00a0can be\u00a0defined as GDSII\u00a0<\/li>\n<\/ol>\n\n\n\n<p>An example of early 3Dblox usage is described here:&nbsp;<a href=\"https:\/\/news.siemens.com\/en-us\/siemens-ase-3dblox-for-vipack\/\" target=\"_blank\" rel=\"noreferrer noopener\">Siemens &amp; ASE collaborate on 3Dblox workflows | Siemens<\/a>&nbsp;<\/p>\n\n\n\n<p>If you are interested to know more about 3Dblox,&nbsp;maybe even&nbsp;explore some examples then please visit this webpage:&nbsp;<a href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/3dblox-resources\/\" target=\"_blank\" rel=\"noreferrer noopener\">3Dblox resources | Siemens Software<\/a>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>If you have not heard of it before, 3Dblox is an emerging standard that was first created by TSMC but is\u00a0now\u00a0managed by IEEE.<\/p>\n","protected":false},"author":71666,"featured_media":1278,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[380,377],"tags":[473,559,475,477,482,471],"industry":[],"product":[535,368],"coauthors":[476],"class_list":["post-1277","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tips-tricks","category-learning-resources","tag-3d-ic","tag-3dblox","tag-chiplet","tag-heterogeneous-design","tag-ic-packaging","tag-semiconductors","product-innovator3d-ic","product-xpedition-ic-packaging"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/64\/2026\/01\/3Dblox_1280x720.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1277","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/users\/71666"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/comments?post=1277"}],"version-history":[{"count":2,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1277\/revisions"}],"predecessor-version":[{"id":1281,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/posts\/1277\/revisions\/1281"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media\/1278"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/media?parent=1277"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/categories?post=1277"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/tags?post=1277"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/industry?post=1277"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/product?post=1277"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/semiconductor-packaging\/wp-json\/wp\/v2\/coauthors?post=1277"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}