3D IC verification requires a golden netlist that allows exceptions

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers need to ensure that the system-level netlist is golden, i.e., it is the absolute reference of system connectivity. When running LVS-type verification between the 3D IC assembly layout and the 3D IC assembly system-level netlist, it is essential that any reported LVS error is related to the physical/logical routing—not the 3D IC netlist. Hence, a high level of confidence is expected in the connectivity information provided by the 3D IC system level netlist. 

Another challenge when verifying the connectivity of a multi-substrate 3D IC design is the project version-based connectivity exceptions, i.e., the need for creating shorts/opens while physically implementing the substrates. Designers need to treat these opens/shorts as “expected” errors and differentiate them from the “real” and “undesirable” errors.

In a recent white paper, Managing system level netlist challenges for 3D IC assemblies in advanced package designs, we present a flow based on the Xpedition Substrate Integrator (xSI) and Calibre 3DSTACK tools that offers a fast, automated, and flexible “netlist versus netlist” approach, so that you can be confident that the system-level connectivity captured in xSI is correct. Additionally, we show that xSI and Calibre 3DSTACK can support known shorts and opens so that connectivity exceptions can be handled seamlessly.

Check out the paper for some “insider” info to begin confidently creating tomorrow’s 3D IC designs today and get a head start on all the advantages this exciting technology can deliver for your company.

Also have a look at my previous blog, 3D IC takes a village but must start with a netlist, where I discuss a workflow that lets the package architect aggregate, construct, and manage a system-level gold netlist that drives all downstream design processes.