Are you new to the realm of high-speed serial channel design? Do you get queasy thinking that a poorly designed via may cause your board to fail? Do you feel like you have to be a SERDES wizard to design up to multi-gigabit speeds? Worry no longer, Siemens has the training course you need.
SERDES 101 to 56 GB/s is a design methodology class that is for digital engineers and layout designers, who are not SI/EMC specialists, to help them successfully design high speed boards on the first pass.
Industry expert, Terry Fox has authored and teaches this class from the perspective of first principles that engineers and layout designers can apply to their designs. Terry is an expert instructor and consultant specializing in ensuring that PCBs pass both signal integrity and EMC requirements the first time. Terry has taught over 500 SI-EMC courses to thousands of students worldwide.
The training course explains how these circuits work. Avoiding mistakes related to these circuits does not guarantee success, but it gives you a much better chance to succeed.
The course also explains how passive elements like PCB materials, via structure, connectors, and blocking capacitors work. You will also go through simulations which will demonstrate how a change in physical structure can result in profound changes in electrical performance.
The course covers active devices — Transmitters and Receivers — and the way each can adjust equalization to make up for some physical channel deficiencies.
Further, the course addresses the various interface standards. You will primarily look at the various agreements within OIF-CEI 4.0. The goal of this section is to help the you understand the relationship between the specification, the specification’s electrical meaning, and the actual performance of the circuit.
The course concludes with a front-to-back example of a 25GB/s design cycle. The design cycle moves through a typical decision flow where we ask questions such as:
- How can we design the board using current technology and meeting physical size limitations?
- Can we use special manufacturing techniques while preserving the board’s economic feasibility?
- What is the effect of various equalization choices?
- What assurance do we have that the finished product will meet a 10x e-15 error rate with a reasonable design and manufacturing margin?
While this is a high speed design methodology class, it is impossible to teach the methodology without simulation tools. For this class we will use HyperLynx SI/PI/Thermal, however, the class is useful even to those students who are not using HyperLynx. If you need tool training, Siemens offers many excellent classes in the HyperLynx product line.
SERDES 101 to 56 GB/s is a 2-day class which is regularly scheduled as a public class. You can also request a private class. Take advantage of Siemens’ event-based pricing which allows you to train up to 12 students for $9,000 USD. That is a savings of over 46%!