Brand New High Speed Design Courses

Mentor Learning Services is proud to announce  a partnership with Terry Fox & Associates offering 2 new classes in the area of High Speed PCB Design. Terry is an industry expert in High Speed Design and delivers courses in his area of expertise to hundreds of students each year. To sign up for these classes, please contact education_services@mentor.com.

Process Implementation: Signal Integrity, Power Integrity and EMC process Implementation (3 days)

SIEMC Process Implementation is three days of face to face class room training or remotely delivered including “hands on” Signal Integrity and Power Integrity simulation labs. Lab exercise designs are a mix of pre-planned and “on the fly” student initiated designs. There is also a very popular “Stump the Professor” session. Present a design structure and find out whether or not there is a valid scientific reason to expect it to work reliably at full speed. Documents published in magazines and sample designs are normally considered to be reliable information. Terry has found them to range from very useful, to dubious, to highly detrimental. Implementing a design without understanding the physics behind the topology is very dangerous. Terry  will explain which of these have a beneficial effect rooted in real science and which ones don’t. We also address organizational process issues.

Key benefits of a design strategy based on the SIEMC Process Implementation:

1. Products function correctly at full speed on the first design build.

2. Products have a high manufacturing yield and a low warranty return rate.

3. The design cycle is predictable. This means, among other things, the products pass EMC regulatory requirements on the first attempt.

This class teaches organizations how to produce “right the first time” designs on a predictable and repeatable basis.

There are three main sections to this process.

1. Document the electrical requirements necessary for a fully functional system.

2. Develop the design rules necessary to insure you meet the electrical requirements.

3. Implement gating check points to assure the design is on track at each stage of development before moving forward.

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Pro Tune Up (1 day):

The purpose of the class is to teach the design methods and validation strategies necessary to assure first time success when implementing modern systems that would typically include, DDR3 / 4, SERDES, LVDS, Gigabit Ethernet, USB 1,2,3, Analog / Digital, Switching Power Supplies, etc.

Pro Tune Up is based on a design methodology developed by a major telecommunications company which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time. “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests on the first try!

Target Audience: Electrical Engineers, FPGA Designers, EMC Certification Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems.

Content:

Basic Signal Integrity including board layer stack-up specification, high speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.

Power Integrity is a lot more than one 0.1uF and two 0.01uF caps per pin. Power integrity depends upon stack-up, capacitor selection, placement, mounting technique, and quantity. Typical target impedance for memory systems must be around 0.1 ohm from DC to the highest frequency of interest. Poor design can result in power impedance poles and inter plane resonances. Many of the mysterious SI and EMI issues can be traced directly to poor power system design.

Root causes and cures for EMI. The goal is to stop the EMI noise at the source. If EMI noise is eliminated at the source, you do not need to chase it around the board. Once you have controlled the noise source, the next issue is to avoid making an efficient antenna. A noisy board with no antenna does not radiate. You need to clearly understand the key reasons for EMI if you want to have any chance of repeatable success.

DDR3 / DDR4 issues. Do you understand the four signal classes which make up a DDR3/4 memory interface. Do you know how to terminate and length match the signals in order to meet timing constraints. Do you know that most published length constraints are ridiculously tight. If you use SODIMM’s, Master Clock, Address, Command, and Control need to be routed with VCC as the reference plane . Do you know why? What constitutes a “safe via?”

Differential Signaling What is the difference between 10/100 Base T Ethernet and LVDS? Are they fundamentally the same or is there a critical difference that can lead to other issues? With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme. However, there can be other nasty complications like Cross Talk and EMI if you do it incorrectly.

SERDES interface routing issues … PCI Express, 10GHz XAUI, Gigabit Serial, etc.. We explain what is important and also debunk some of the popular myths about routing these types of interfaces. Do you understand how vias can cause a non-phase coherent channel?

Analog Digital Interface i.e. Isolation vs. Communication There are many ways you can do this, but only one is easy to understand and produces repeatably good results. How do you control EMI if you need to have long leads on isolated inputs?

Quiet DC to DC Switchers There are many voices in the technological wilderness. I teach a method that keeps these things from contaminating the rest of your design.

To Moat or Not To Moat..That is the question! Slicing up the ground plane has caused more problems than I can count. Do you know how to analyze these issues?

Proper Grounding Practice Can you explain how signal ground should be connected to chassis ground and why?

Connectors, Board to Board, Board to cable, etc. What are the SI, EMI, and Power Issues. When we get to the connector, we still need to deal with physics.

Basic Shielding & Filter Theory as it applies to Enclosures, Switching Power Supplies, and Renegade ChipsCritical elements in an effective high speed system design process. Simply performing a solid pre-layout design review and including the correct personnel can raise you first time odds of success to at least 65%. Adding the post-layout design review can result in first time success 90%+ even the first time you go through the process. Getting from 90% to 99% “right the first time” results is simply a matter of practice if you use methods based in real physics.

About Terry Fox – BSEE Montana State University 1969

After serving in the US Navy as a pilot and aircraft maintenance officer, Terry began his professional career in 1972 as a Hewlett Packard electronic instrument Field Engineer selling and supporting products ranging from DC to Microwave. During the Gate Array revolution of the mid 80’s Terry joined the Daisy team selling circuit simulation and physical design layout tools. In 1995 Terry began selling UniCAD Signal Integrity and EMC prediction tools. 

In 2004 Terry started offering public Signal Integrity and EMC classes throughout North America. He teaches 40 public classes and roughly 5-10 private classes each year in addition to his consulting practice. Terry has taught over 500 SI EMC classes to thousands of students and hundreds of companies always with the same message: build it right the first time, it is the best investment you can make.

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