Functional Verification Training Team is featured in this post. Massoud, Chris and Shaimaa are responsible for development and delivery of courses in the functional verification domain. They use the inputs and expertise from various other divisions in Mentor to create quality content.
Massoud Eghtessad is a Principal Instructional Designer and Technical Trainer and is deeply knowledgeable of Mentor’s tools and best practices, having provided technical support and training to customers for over ten years. He has worked with global customers to help them succeed with ASIC design and verification, SystemVerilog, Verilog and VHDL Modeling and simulation, UVM and use of Mentor’s verification products among many other specializations. He is the team lead for the verification training team and develops and teaches several functional verification courses. Among his past experience, Massoud was a Senior Applications Consultant and ASIC Verification Products Specialist at Synopsys, Inc., providing tool and methodology support and training to users of verification flows and products. Massoud holds an MS in Computer Engineering from Northeastern University, has achieved Technical Training Certification in CompTIA and CTT+, and is motivated by coaching customers to success in cutting edge design technologies. Massoud is also well versed in instructional design and adult learning theories and practices.
Chris Spear is a Principal Instructional Designer and Technical Trainer and brings over twenty five years of EDA expertise to Mentor customers. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant with Synopsys. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. His paper on UVM Coding Guidelines was voted second best of conference at DVCon 2020. Outside of work, you may see Chris bicycling over 12,000-foot mountain passes.
Shaimaa Yehia is a Senior Instructional Designer and Technical Trainer. As an instructional designer, Shaimaa has used her vast technical background to develop content for several on-demand and classroom courses in functional verification, emulation and design solution domains. This includes courses for Veloce, ModelSim/Questa Simulation, HDL Design Series, Visualizer, SystemVerilog and UVM. She also delivers a number of these courses to users of these products and methodologies. Shaimaa holds a bachelor’s degree in communication and Electronics Engineering with honors, from Ain-Shams University, Egypt.