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Tips for Deciphering DDR Simulation Results

So you’ve finished your simulation, and you have the results. For a DDR bus, this…

DDR Design: Write leveling for better DQ timing

So far, we’ve gone through the basics of the DDR Bus, and discussed some of…

Receiver requirements in DDR design

Once we have a topology for the data and address busses in mind or have…

What causes undesirable SI in DDR designs?

Continuing my blog series on DDR [Part 1 – Controlling DDR, Part 2 – Memory…

The Back and Forth of the DDR Data Bus

So far, this blog series has discussed the stress of DDR design and introduced the DDR…

Understanding the DDR memory bus

In the first blog in my series about DDR design, I talked about the stress…

Take Control of DDR Stress

Designing a high-speed bus can be stressful. Wide, high-speed busses, such as DRAM DDR memory…

Accuracy in HyperLynx

I frequently get asked, “what is the maximum frequency that you can simulate in HyperLynx?” …

The Simulation Advantage

The advent of high-speed serial links added many challenges to the process of designing PCBs. …