HyperLynx VX.2.4 is available for download!

Have you downloaded it yet? A single download now installs HyperLynx SI/PI/Thermal, HyperLynx DRC and…

SerDes Design Part 7: ERL vs RL, the Move Toward More-Effective Characterization Metrics

Ever heard of ERL? If not, you soon will. Effective Return Loss (ERL) is a…

Is Your PCB Layout Correct by Design? Differential Phase Matching Could Be the Answer.

One of the most important benefits of HyperLynx DRC is its ability to look for…

Chalk Talk: Suppressing Noise from Via-to-Via Coupling

Like Cristian Filip who recently spoke on SerDes design, I just did my first Chalk…

SERDES Channel Compliance: Easier Said than Done?

Data transfers can be done in two distinct ways, parallel (DDR2/3) and serial (PCIE/USB). As…

Chalk Talk: SerDes Design

Recently, I had the chance to work with Amelia Dalton, news editor at Techfocus Media,…

Low-Power Designs Need Signal Integrity Analysis

Ask any signal integrity expert, what keeps you awake at night? Most will agree that…

Are All Post-Layout PCB Design Rule Checkers Created the Same?

The answer is a resounding NO! To prove it, we’re giving away eight electrical DRCs…

Don’t Forget the Basics! Always Check for T-Fork Topology.

DDR memories allow the transfer of data at a higher speed than most other memory…