Take Control of DDR Stress

Designing a high-speed bus can be stressful. Wide, high-speed busses, such as DRAM DDR memory busses, can be especially…well, memorable. While the schematic design for such busses may be somewhat simple – after all, it’s just wiring up one pin to another – the layout and bring-up phases will be less so.

There are two broad reasons for this complexity which I discussed in my article ‘Designing PCBs for DDR Busses.’

The first is the arch-nemesis of all high-speed parallel busses: speed. As signals get faster, they become more finicky and quirky. At slower speeds, the transmitter can simply send a voltage to represent a one, and zero volts to represent a zero, and be confident that the receiver got the message.

At higher speeds, however, this isn’t a given.

If the channel is long, then time is needed for the signal to traverse from the transmitter to the receiver. This energy, if not correctly dissipated, can alter the signal of subsequent bits – an effect known as Inter Symbol Interference (ISI).

Changing voltages and currents can create voltages and currents in neighboring channels. This means that a signal on one channel can create unintended energy (called “crosstalk noise”) in neighboring channels. Parallel busses, such as the DDR bus, are more susceptible to crosstalk because most of the signals are single-ended.

In addition to signal integrity challenges such as ISI and crosstalk on the DDR bus, it can also be difficult to know what to validate in the first place.

For the DRAMs, validation requirements are spelled out in the JEDEC documentation. However, these documents aren’t always a fun read and they can be confusing to new readers. Remember, it’s a committee of competing companies that came up with the document. So, “easy reading” isn’t usually at the top of their priority list when generating the document.

On the controller side, the validation requirements are usually more straightforward as it’s in the best interest of the controller vendor for designs to be completed quickly and with high quality. Nevertheless, it is still up to the designer to make sure that the document and the requirements are well understood.

So, how can a poor designer tame the complexities of signal integrity and the mysteries of validation requirements?

Enter Simulation. Simulation tools such as HyperLynx® are designed specifically to tackle these issues. HyperLynx goes through the physics of your board and generates waveforms (including signal integrity effects) at the appropriate locations. It then goes on to decipher whether the waveforms indicate good quality or a channel that will give nothing but problems when it is fabricated.

In my upcoming blogs, I will discuss how best to design the DDR bus with these considerations in mind.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/hyperlynx/2017/08/29/take-control-of-ddr-stress/