In the past I have blogged about crossing splits in reference planes. This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.
But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via. In such a case, the reference planes will change and the return current will need to find a path to accomodate the change. This is probably best explained with a picture, which can be seen (along with a more complete explanation) in my recent article in PCDandF: http://pcdandf.com/cms/component/content/article/171-current-issue/9656-designers-notebook
This problem is most severe for very fast, single-ended signals like DDR3 or DDR4, which will have all their return current present in their reference planes, and require a very close-by stitching via (or capacitor) in order to ensure minimal radiation of signal energy and minimal resulting signal degradation. The further away the stitching via (or cap), the more energy that will radiate and the more degraded the signal will become. SERDES signals, although much faster, also happen to be differential, which means that they tend to have mostly self-contained, zero net return current (since they consist of equal and opposite signals).
So, every time you transiton between signal layers, try to add a stitching via as well. If you are wondering how many un-stitched transitions you have in your design, run the Vertical Reference Plane Change DRC in HyperLynx DRC and it will find them for you…