Vias are longer than their length

Yeah, that’s what I said.  Vias are longer than their length.  Phrased more appropriately, the delay introduced by a via has a lot more to it than just the length of the via.  For starters, signals propagate through vias much differently than they propagate through traces.  So trying to length match and include “via lengths” doesn’t make much sense in your layout.  If you really wanted to be precise enough to include the lengths of vias in your length-matching requirements you should just simulate the flight time of the entire net.  That would give you the real picture, including all the interactions between the trace impedance and the via impedance.  But, if you don’t want to go that far, at least simulate to get through the delay of the via and turn that into an equivalent “trace length” to use in your calculations.  In either case, it doesn’t make sense to use the actual via length.

Another issue to be aware of is that of stubs on the vias.  Stubs will serve to add extra capacitance, which will slow down the edge and introduce even more delay.  So, a longer via may actually introduce less delay than a “shorter” via.  This issue, as well as some others concerned with length constraints and timing, are discussed in my recent article in EETimes:
http://www.eetimes.com/design/signal-processing-dsp/4212315/Meeting-timing-specs-on-boards-with-picoseconds-of-margin-semiconductor

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/hyperlynx/2011/01/27/vias-are-longer-than-their-length/