Master the design and verification of next gen transport: Part One – overview

By nileshthiagarajan

Excerpt from article: “Master the design and verification of next gen transport: Part One – overview

The role of high-level synthesis

HLS is a ‘shift left’ abstraction above RTL. Some of the main advantages claimed for it include:

-An ability to generate high quality RTL from descriptions in C++ and System C, that also allows for wide architectural exploration pulling upon IP libraries and all of this achieved much more quickly than hand-coding RTL alone (an increasingly onerous task as design sizes mushroom).

-Much faster simulation speeds, anything between 50 and 1,000X faster than for traditional simulation, with verification further assisted by formal pre-RTL synthesis checks and increasingly robust metrics for code and functional coverage.

-Integrated power optimization, and equivalence checking across C++ models and the resulting RTL.

Each of these qualities has benefits in terms of the challenges facing automotive design.

They accelerate design cycles, reducing code volume by 5X compared to RTL. Users can quickly swap new features in and out. They can examine their coding and architectural options, and optimize across power, performance and area. On that last point, as well as facing the challenge of implementing more sophisticated algorithms, ADAS systems overall face a power ceiling of just 100W.

Read the entire article on TechDesignForum originally published on September 30th, 2019.

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This article first appeared on the Siemens Digital Industries Software blog at