{"id":1320,"date":"2019-03-28T10:22:06","date_gmt":"2019-03-28T17:22:06","guid":{"rendered":"https:\/\/blogs.mentor.com\/expertinsights\/?p=1320"},"modified":"2026-03-26T16:13:59","modified_gmt":"2026-03-26T20:13:59","slug":"article-roundup-5g-deep-learning-embedded-interrupts-hardware-centric-hls-code-checking-faster-post-silicon-debug-test","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/expertinsights\/2019\/03\/28\/article-roundup-5g-deep-learning-embedded-interrupts-hardware-centric-hls-code-checking-faster-post-silicon-debug-test\/","title":{"rendered":"Article Roundup: 5G, Deep Learning, Embedded Interrupts, Hardware-Centric HLS Code Checking &amp; Faster Post-Silicon Debug &amp; Test"},"content":{"rendered":"<ol>\n<li><strong><a href=\"https:\/\/semiengineering.com\/gearing-up-for-5g\/\" target=\"_blank\" rel=\"noopener\">Gearing Up For 5G<\/a><\/strong><\/li>\n<li><strong><a href=\"https:\/\/www.electronicdesign.com\/embedded-revolution\/delving-deep-learning\" target=\"_blank\" rel=\"noopener\">Delving into Deep Learning<\/a><\/strong><\/li>\n<li><strong><a href=\"https:\/\/www.embedded.com\/design\/operating-systems\/4461604\/Interrupts-in-the-Nucleus-SE-RTOS?_mc=sm_emb\" target=\"_blank\" rel=\"noopener\">Interrupts in the Nucleus SE RTOS<\/a><\/strong><\/li>\n<li><strong><a href=\"https:\/\/www.techdesignforums.com\/blog\/2019\/02\/26\/a-hardware-centric-approach-to-checking-hls-code-before-synthesis\/\" target=\"_blank\" rel=\"noopener\">A hardware-centric approach to checking HLS code before synthesis<\/a><\/strong><\/li>\n<li><strong><a href=\"https:\/\/www.semiwiki.com\/forum\/content\/8012-accelerating-post-silicon-debug-test.html\" target=\"_blank\" rel=\"noopener\">Accelerating Post-Silicon Debug and Test<\/a><\/strong><\/li>\n<\/ol>\n<p><strong><\/strong><br \/>\n<strong><\/strong><\/p>\n<p><strong><a href=\"https:\/\/semiengineering.com\/gearing-up-for-5g\/\" target=\"_blank\" rel=\"noopener\">Gearing Up For 5G<\/a><\/strong><br \/>\n<em>SemiEngineering<\/em><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-1321 alignright\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/49\/2019\/03\/5G-network-man-holds-phone-Adobe-39552117-1-520x347.jpg\" alt=\"\" width=\"348\" height=\"232\" \/> 5G is expected to jumpstart exciting new capabilities in several markets including automotive, mobile, and the IoT. The new wireless standard will provide orders of magnitude improvements in communication speed and latency, leaving systems companies to decide whether to process their data locally or in the cloud. The choice these companies make will, to a certain degree, determine semiconductor architecture decisions going forward, from processor and memory to power budgets and more.<\/p>\n<p><strong><\/strong><br \/>\n<strong><\/strong><\/p>\n<p><strong><a href=\"https:\/\/www.electronicdesign.com\/embedded-revolution\/delving-deep-learning\" target=\"_blank\" rel=\"noopener\">Delving into Deep Learning<\/a><\/strong><br \/>\n<em>Electronic Design<\/em><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-1322\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/49\/2019\/03\/Ai-brain-shaped-circuit-on-board-Adobe-206246882-520x347.jpg\" alt=\"\" width=\"344\" height=\"229\" \/> What is deep learning? According to Chris Rowen, CEO of BabbleLabs, it is \u201cthe construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.\u201d But, Rowen contends that an understanding of how deep learning differs from AI and machine learning is important to fully understand deep learning and its implications at the application level. Rowen spoke on this topic at a recent summit hosted by Mentor\u2019s Emulation Division.<\/p>\n<p><strong><\/strong><br \/>\n<strong><\/strong><\/p>\n<p><strong><a href=\"https:\/\/www.embedded.com\/design\/operating-systems\/4461604\/Interrupts-in-the-Nucleus-SE-RTOS?_mc=sm_emb\" target=\"_blank\" rel=\"noopener\">Interrupts in the Nucleus SE RTOS<\/a><\/strong><br \/>\n<em>Embedded.com<\/em><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignright size-full wp-image-1325\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/49\/2019\/03\/RTOSRevealed290.jpeg\" alt=\"\" width=\"290\" height=\"249\" \/> Interrupts in microprocessors and microcontrollers provide the responsiveness necessary for many applications. However, this can conflict with the functioning of a real-time operating system that also aims to be responsive and predictable. Colin Walls explains how Nucleus SE handles interrupts to address this conflict.<\/p>\n<p><strong><\/strong><br \/>\n<strong><\/strong><\/p>\n<p><strong><a href=\"https:\/\/www.techdesignforums.com\/blog\/2019\/02\/26\/a-hardware-centric-approach-to-checking-hls-code-before-synthesis\/\" target=\"_blank\" rel=\"noopener\">A hardware-centric approach to checking HLS code before synthesis<\/a><\/strong><br \/>\n<em>Tech Design Forum<\/em><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-1323\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/49\/2019\/03\/designcheckerflow_HLS-520x366.jpeg\" alt=\"\" width=\"344\" height=\"242\" \/> Traditionally, finding issues in C++ or SystemC code before passing it to high level synthesis (HLS) was tricky, potentially slowing the adoption of HLS. The crux of the problem is that static software analysis tools were not designed to understand hardware intent. Now, a new hardware-centric combination of static and formal verification techniques resolves the main limitations of previous approaches.<\/p>\n<p><strong><\/strong><br \/>\n<strong><\/strong><\/p>\n<p><strong><a href=\"https:\/\/www.semiwiki.com\/forum\/content\/8012-accelerating-post-silicon-debug-test.html\" target=\"_blank\" rel=\"noopener\">Accelerating Post-Silicon Debug and Test<\/a><\/strong><br \/>\n<em>SemiWiki<\/em><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignright wp-image-1324\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/49\/2019\/03\/Figure-2-Traditional-Test-Flow-520x248.jpg\" alt=\"\" width=\"346\" height=\"165\" \/> SoC designers are using more embedded IP, creating a challenge for post-silicon bring up and slowing time-to-market. This is partially due to the inherent inefficiencies of current silicon bring-up and debug flows that involve multiple transitions of test collateral. This article examines a new flow that enables DFT engineers to observe IP directly in the SoC under test.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Gearing Up For 5G Delving into Deep Learning Interrupts in the Nucleus SE RTOS A hardware-centric approach to checking HLS&#8230;<\/p>\n","protected":false},"author":71673,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[],"industry":[],"product":[],"coauthors":[],"class_list":["post-1320","post","type-post","status-publish","format-standard","hentry","category-news"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/posts\/1320","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/users\/71673"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/comments?post=1320"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/posts\/1320\/revisions"}],"predecessor-version":[{"id":2126,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/posts\/1320\/revisions\/2126"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/media?parent=1320"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/categories?post=1320"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/tags?post=1320"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/industry?post=1320"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/product?post=1320"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/expertinsights\/wp-json\/wp\/v2\/coauthors?post=1320"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}