In the past\u00a0I have blogged about crossing splits in reference planes.\u00a0 This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.\u00a0<\/p>\n
But another type of reference plane change which is more common, and usually\u00a0much less avoidable,\u00a0is when a signal transitions layers through a via.\u00a0 In such a case, the reference planes will change and the return current will need to find a path to accomodate the change.\u00a0 This is probably best explained with a picture, which can be seen (along with a more complete explanation) in my recent article in PCDandF: http:\/\/pcdandf.com\/cms\/component\/content\/article\/171-current-issue\/9656-designers-notebook<\/a> So, every time you\u00a0transiton between signal layers, try to add a stitching via as well.\u00a0 If you are wondering how many un-stitched transitions you have in your design, run the Vertical Reference Plane Change DRC in HyperLynx DRC and it will find them for you…<\/p>\n","protected":false},"excerpt":{"rendered":" In the past\u00a0I have blogged about crossing splits in reference planes.\u00a0 This is probably the most glaringly obvious of reference…<\/p>\n","protected":false},"author":71672,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[13],"tags":[1035,1036,1049,1064,1104,1107,1126,1127,1129],"industry":[],"product":[],"coauthors":[],"class_list":["post-971","post","type-post","status-publish","format-standard","hentry","category-news","tag-ddr3","tag-ddr4","tag-drc","tag-hyperlynx-drc","tag-reference-plane","tag-return-current","tag-stitching-cap","tag-stitching-capacitor","tag-stitching-via"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/971","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/71672"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=971"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/971\/revisions"}],"predecessor-version":[{"id":10350,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/971\/revisions\/10350"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=971"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=971"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=971"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=971"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=971"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=971"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nThis problem is most severe for very fast, single-ended signals like DDR3 or DDR4, which will have all their return current present in their reference\u00a0planes, and require a very close-by stitching via (or capacitor) in order to ensure minimal radiation of signal energy and minimal resulting signal degradation.\u00a0 The further away the stitching via (or cap), the more energy that will radiate and the more degraded the signal will become.\u00a0\u00a0 SERDES signals, although much faster, also happen to be differential, which means that they tend to have mostly self-contained, zero net return current (since they consist of equal and opposite signals).<\/p>\n