{"id":9618,"date":"2023-06-27T08:00:00","date_gmt":"2023-06-27T12:00:00","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/?p=9618"},"modified":"2026-03-27T09:41:35","modified_gmt":"2026-03-27T13:41:35","slug":"signal-integrity-analysis","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2023\/06\/27\/signal-integrity-analysis\/","title":{"rendered":"PCB design best practices: signal integrity analysis"},"content":{"rendered":"\n

As a part of pillar three, digital prototype-driven verification<\/a>, let’s dive into signal integrity analysis.<\/p>\n\n\n\n

What is signal integrity analysis?<\/h2>\n\n\n\n

PCB signal integrity is the study of the analog switching behavior of high-speed digital signals. We like to think of digital signals as the square waves we see in logic timing diagrams, but that\u2019s now how they look in real life \u2013 they\u2019re far messier, often to the point of being unrecognizable as digital signals. That happens because how we place components and route signals affects how those signals behave, if the devices are fast enough. Bottom line \u2013 if it matters how the components get placed and the trace gets routed \u2013 you\u2019ve crossed into the realm of requiring signal integrity.<\/p>\n\n\n\n

How does someone know they need signal integrity analysis?<\/h2>\n\n\n\n

When we send a signal out from a driver down a trace towards a receiver, we\u2019d like to think the signal travels to the receiver and simply stops \u2013 a nice clean edge. But that\u2019s not how electromagnetic waves work \u2013 while they do propagate and eventually settle out, the details matter. We begin to see issues when the ratio of the driver\u2019s edge rate to the trace\u2019s electrical length reaches a critical value. If the driver\u2019s edge rate is slow enough, the signal has plenty of time to propagate and settle down, so the signal\u2019s behavior appears to be the same everywhere on the trace. Think of a long, narrow rectangular pool \u2013 if you pour water into one end slowly enough, the water appears to rise evenly all through the pool\u2019s length. However, if you pour a lot of water in all at once, you\u2019ll see a very clear wavefront going out from where your end, sloshing back and forth in the pool until things eventually settle down.<\/p>\n\n\n\n

The critical point where you need to start thinking about signal integrity \u2013 is when the driver\u2019s edge rate is about 1\/6 the electrical length of the net. That lets the signal propagate down to the receiver and back to the driver 3 times during an edge \u2013 slow enough, generally, to prevent \u201csloshing\u201d.   If the driver\u2019s edge rate is any faster than that, then we start to see the kinds of effects (reflections, ringing, crosstalk) that require signal integrity analysis to evaluate and mitigate.<\/p>\n\n\n\n

That\u2019s a simple overview, of course \u2013 as edge rates decrease and data bit rates increase, the physical phenomena that need to be considered become increasingly complicated \u2013 and the analysis increasingly sophisticated \u2013 to the point where much of the signal integrity simulation that gets run today is performed by dedicated specialists who run signal and power integrity simulations full-time.<\/p>\n\n\n\n

What\u2019s not working today?<\/h2>\n\n\n\n

Most of the signal integrity analysis that gets performed today is run by full-time specialists; they\u2019re dedicated to those tasks.  The problem is, there are far too few specialists to service way too many PCBs being designed. With the definition of \u201chigh-speed\u201d from, virtually every net on every board these days can be considered \u201chigh-speed\u201d \u2013 and there\u2019s no way all those nets on all those boards can be analyzed.<\/p>\n\n\n\n

To deal with the \u201cSI expert crunch\u201d, most systems companies have adopted two design approaches:<\/p>\n\n\n\n

    \n
  1. Pre-route design space exploration (use of signal integrity analysis tools to determine an optimal placement and routing strategy) is only performed where absolutely required. The preferred method is to place and route the design based on guidelines supplied by the component vendors, which assumes that the vendors have, in fact, done those studies and that the board design assumptions they made (stackup, board size, etc.) are applicable to the customer\u2019s intended application. In theory, this approach works fine \u2013 but in practice, the \u201cone size fits all\u201d approach to design rules drives up board costs. Additionally, vendor layout rules often get bent or broken and those issues often don\u2019t get caught until a board is in the lab.<\/li>\n\n\n\n
  2. Post-route design verification (simulation of the board as-designed to determine operating design margins) is often minimal or non-existent. The processes most systems companies use for post-layout signal integrity analysis are labor-intensive, and there just isn\u2019t time for that. So \u2013 most companies settle for a visual design review, and if post-layout simulation is performed at all, it\u2019s limited to a handful of signals that are meant to cover the extremes \u2013 the shortest net, the longest net, and so on. The problem is \u2013 layout problems creep in randomly; you can\u2019t rely on being able to pick the signals where problems occur, so this approach lets layout problems slip through to prototype manufacturing. That means problems are discovered and debugged in the lab, and the board must be respun.<\/li>\n<\/ol>\n\n\n\n

    What are the roadblocks?<\/h2>\n\n\n\n

    Signal integrity analysis, traditionally, has been a process implemented by (with EDA tools designed for) dedicated specialists. As the technical challenges have become tougher, analysis tools have become more sophisticated and difficult to use. It\u2019s easy to produce results with a simulator \u2013 but it\u2019s not always easy to produce results that reflect how a design will really work. Because the state of the art in signal integrity moves so fast, most analysis tools have focused solely on solving the \u201cstate of the art\u201d problems, leaving usability as a problem to be addressed later. The problem is \u2013 \u201clater\u201d never comes, so the tools become more complex, hard to use and prone to producing erroneous results if not set up by an expert user.<\/p>\n\n\n\n

    And so \u2013 the gulf between what simulation specialists can run and the simulations that need to be run continues to grow. Here again, the \u201cone size fits all\u201d approach is the problem \u2013 most EDA tools are developed as though state-of-the-art analysis was the only problem, when in fact, most designs (and potential users) would be better suited by tools that were somewhat less sophisticated but considerably more usable.<\/p>\n\n\n\n

    Let\u2019s consider an analogy in the automobile industry. If speed were the ONLY thing that mattered, then it would make sense to say that all cars should be Lamborghinis, or an equivalent. But while Lamborghinis are fantastic cars, they\u2019re not very practical for taking the kids to their soccer game, driving in the snow in New York City, or hauling wood home from the lumberyard. One size fits all doesn\u2019t work for automobiles; it\u2019s time we realized that approach doesn\u2019t work for signal and power integrity analysis either.<\/p>\n\n\n\n

    Because signal integrity is practiced by relatively few people, it is poorly understood by many, with an associated set of myths. To list a few:<\/p>\n\n\n\n