{"id":9503,"date":"2023-03-31T13:30:24","date_gmt":"2023-03-31T17:30:24","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/?p=9503"},"modified":"2026-03-27T09:39:01","modified_gmt":"2026-03-27T13:39:01","slug":"why-you-should-attend-user2user-north-america","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2023\/03\/31\/why-you-should-attend-user2user-north-america\/","title":{"rendered":"Why you should attend User2User – North America"},"content":{"rendered":"\n

This one-day Siemens EDA User Group Meeting at the Santa Clara Marriott on Thursday, April 13th is your opportunity to hear from other Xpedition, HyperLynx, Xpedition IC Packaging, and Valor customers as well as industry experts on how to achieve design success and gain a competitive advantage.<\/p>\n\n\n\n

Admission and parking for U2U is free and includes all technical sessions, lunch, and a networking reception at the end of the day.<\/p>\n\n\n\n

Preview our sessions:<\/h2>\n\n\n\n
\"Andy<\/figure>
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Development leap in automotive electronics using chiplets<\/strong><\/p>\n\n\n\n

Presenter: Andy Heinig<\/strong> <\/strong>Head of Department, Fraunhofer IIS\/EAS<\/em><\/strong><\/strong><\/p>\n\n\n\n

A major driver for the future of electronic systems is expected to be chiplets — an evolution from SoCs to a solution consisting of different IC technologies. For automotive electronics, this can pave the way for a development leap because the newest nodes can be brought to application much faster. This presentation will showcase the development starting from system architecture exploration, to high-level FPGA-based implementations and down to system integration using XSI.<\/p>\n<\/div><\/div>\n\n\n\n

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\"Dr.-Jawad-Nasrullah-CEO-Palo-Alto-Electron_200\"<\/figure>
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Chiplet modeling and workflow standardization through CDX<\/strong><\/p>\n\n\n\n

Presenter: Dr. Jawad Nasrullah CEO, Palo Alto Electron<\/strong><\/p>\n\n\n\n

The CDX workstream at OCP\/ODSA aims to establish standards for commercial chiplet design, promoting modularity and efficiency. This talk will cover CDX’s proposed chiplet modeling requirements, necessary design automation workflows, and the importance of multi-physics design optimization in the early stages of chiplet planning. Achieving the full benefits of ‘chipletization’ requires exploring, optimizing, and architecting these factors from the outset.<\/p>\n<\/div><\/div>\n\n\n\n

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\"Matthew-Monroe-Package-Design-Engineer-Micron\"<\/figure>
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A novel strategy to mixed memory system-in-package co-design<\/strong><\/p>\n\n\n\n

Presenter: Matthew Monroe Package Design Engineer, Micron<\/strong><\/p>\n\n\n\n

Dedicated EDA software has enhanced 2.5\/3D and SoC packaging workflows to evaluate system-level trade-offs related to floorplanning and routability, enabling reduced costs, cycle-time, and design errors. However, unknowns exist when considering heterogenous integration related to System-in-Package (SiP). This paper, for the first time, benchmarks complex co-design challenges specific to mixed-memory SiP development.<\/p>\n<\/div><\/div>\n\n\n\n

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\"Todd-Snider-Software-Application-Engineer-Intel-Corporation\"<\/figure>
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Package design circuit block reuse methodology<\/strong><\/p>\n\n\n\n

Presenter: Todd Snider Software Application Engineer, Intel Corporation<\/strong><\/p>\n\n\n\n

As product and packaging technologies evolve and advance in complexity, the need for a modular design layout methodology increases. Creating and perfectly replicating repeated patterns within IP block break out at 1st level interconnect regions, from 2nd level interconnect up to routing layers, and for those features in between is critically important to Power and Signal integrity. In addition, the need to systematically modify a source pattern and update the instances of a given pattern, is a powerful time saving feature that ensures high quality with minimal impact to design progression.<\/p>\n<\/div><\/div>\n\n\n\n

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\"Jayaprakash-Balachandran-Technical-Lead-Engineer-Cisco-Systems\"<\/figure>
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Streamlining stackup planning with Z-planner Enterprise<\/strong><\/p>\n\n\n\n

Presenter: Jayaprakash Balachandran\u00a0Technical Lead Engineer, Cisco Systems<\/em><\/strong><\/p>\n\n\n\n

Any process that consumes considerable time without adding value to the end product is ripe for replacement. Before Z-planner Enterprise, Cisco\u2019s stackup workflow was at that point. Our advanced technologies necessitates that we lock down our stackup details internally to ensure that they don\u2019t change between our fabricators. Z-planner Enterprise streamlines our stackup validation process, aligning directly with our DRC. We can now evaluate three different stackups in an hour rather than a day.<\/p>\n<\/div><\/div>\n\n\n\n

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Performing DFM concurrent with design<\/strong><\/p>\n\n\n\n

Presenter: Jose Martinez\u00a0Application Engineer, Siemens<\/em><\/strong><\/p>\n\n\n\n

DFM has evolved from a tool only manufacturers use, to one embraced by all. Leading OEMs have streamlined their DFM process by implementing it within the design process, leveraging the advantages of resolving issues at the earliest possible stage. I address the evolution of DFM into a concurrent tool and suggest simple steps for a successful implementation across a design process. With concurrent DFM, a new PCB design can be released to manufacturing without any issues, the first time.<\/p>\n<\/div><\/div>\n\n\n\n

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Integrated PI analysis workflows for package design<\/strong><\/p>\n\n\n\n

Presenter: John Medina\u00a0Senior Package Designer, Chipletz<\/em><\/strong><\/p>\n\n\n\n

This session will review analysis flows that can improve the productive of the package design process. We will use XPD to assign embedded passive components to rails and calculates current per device from a given current level for that rail. Using this, we will use integration with Xpedition Package Designer (XPD) and HyperLynx PI to identify DC power issues in package designs from within XPD. This allows designers to check for voltage and current issues while designing the substrate.<\/p>\n<\/div><\/div>\n\n\n\n

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Verification and correlation of a C-Phy Flex\/Rigid PCB<\/strong><\/p>\n\n\n\n

Presenter: Grace Yu\u00a0Senior SIPIEMC Manager, Meta Platforms, Reality Labs<\/em><\/strong><\/p>\n\n\n\n

This session will explore a simulation and automation methodology using HyperLynx Advanced Solvers and HyperLynx Signal Integrity. The methodologies address the challenges from complicated C-PHY channels consisting of multiple rigid-flex printed circuit board connections. We will validate the passive channel characteristics using HyperLynx Signal Integrity against the C-Phy channel specification.<\/p>\n<\/div><\/div>\n\n\n\n

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Feasibility of PCle Gen4 in automotive trucking application<\/strong><\/p>\n\n\n\n

Presenter: Patrick McNamara\u00a0Staff Electrical Engineer, TuSimple<\/em><\/strong><\/p>\n\n\n\n

Safety is a top priority concern in today\u2019s automotive designs. A method being investigated is reducing reaction time for sensor data to be computed and then deliver control messages. One of the methods is using PCIe Gen4 as the communication backbone between sensors, GPU, and CPU. In order to make a calculated decision, several factors were considered for optimization including S-Parameter models to determine a power budget which provide downstream packaging decisions for mechanical and thermal considerations<\/p>\n<\/div><\/div>\n\n\n\n

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10 things you need to know about Copper Roughness & Signal Integrity<\/strong><\/p>\n\n\n\n

Presenter: Bill Hargin\u00a0CEO, Z-zero<\/em><\/strong><\/p>\n\n\n\n

There’s been a lot of talk over the years regarding copper roughness, yet few hardware engineers or signal integrity practitioners have a detailed understanding of this key contributor to high-speed signal loss. To keep you from getting surprised by previously untracked contributors to insertion loss, we will discuss 10 critical things you need to know about copper roughness and their impact on board costs and signal integrity.<\/p>\n<\/div><\/div>\n\n\n\n

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Model based design: Bridging systems & electronics design domain<\/strong><\/p>\n\n\n\n

Presenter: David Kirlew\u00a0Manager Electrical Engineering, Moog<\/em><\/strong><\/p>\n\n\n\n

Advancements in Model Based Computer Aided Design are bridging systems and design domain knowledge into a higher performance and cost-effective development environment. This presentation explores the capabilities of the Siemens Model Based Designs (MBD) tools (Teamcenter, Engineering Data Management (EDM), Xpedition and System Model Workbench (SMW)) in the development processes of a simple Solenoid Operated Valve (SOV) control electronic design within the digital thread.<\/p>\n<\/div><\/div>\n\n\n\n

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Eliminate design spins by shifting validation earlier<\/strong><\/p>\n\n\n\n

Presenter: Nick Barbin\u00a0President, Optimum Design<\/em><\/strong><\/p>\n\n\n\n

Best-practice design processes validate early and often to minimize re-spins and actually shorten the overall design cycle. This shift-left approach enables design engineers and layout designers to validate within their native environment, minimizing the bottleneck waiting for specialist reviews, and freeing the specialists to resolve the remaining critical issues. This session will look at examples of analysis and verification deployed throughout the design process.<\/p>\n<\/div><\/div>\n\n\n\n

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As an added bonus, EDA visionaries and thought leaders will also share new and emerging trends, ideas, and advances in technology in a series of mini-keynotes during the General Session Luncheon.<\/p>\n\n\n\n

April 13, 2023: 11:45am – 1:30pm<\/strong><\/p>\n\n\n\n

Register for User2User today!<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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