{"id":9198,"date":"2010-01-14T13:44:24","date_gmt":"2010-01-14T20:44:24","guid":{"rendered":"https:\/\/blogs.mentor.com\/hyperblog\/?p=124"},"modified":"2026-03-27T09:17:10","modified_gmt":"2026-03-27T13:17:10","slug":"ami-the-next-modeling-frontier","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2010\/01\/14\/ami-the-next-modeling-frontier\/","title":{"rendered":"AMI – The next modeling frontier"},"content":{"rendered":"

If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI – Algorithmic Modeling Interface.\u00a0\u00a0 AMI is essential a fast behavioral model of multi-gigabit transmitters and receivers.\u00a0\u00a0 Standard IBIS models are good for regular switching edges up to some surprisingly fast speeds, but when you start adding in things like pre-emphasis, and equalization on those edge, the old IBIS I-V tables just don’t cut it any more.\u00a0 So how do you account for those kinds of behaviors?\u00a0 There are options, but the most common today is SPICE, and not just any ol’ SPICE, it’s typically HSPICE encrypted models because that’s the easiest thing for an IC company to deliver.\u00a0 That means that you’re locked into one vendor for your signal integrity simulation – that’s generally not good for you and not good for the industry either.<\/p>\n

So out of this need drove the creation of AMI.\u00a0 AMI was approved as part of the IBIS 5.0 modeling specification<\/a> and was designed to characterize things like pre-emphasis, equalization, clock recovery, etc in a transceiver.\u00a0 Beyond just the characterization, the intent of AMI is to deliver fast time domain simulation results on a vendor independent platform (this is nothing new for IBIS – it’s been the standards mantra since its inception).\u00a0 There’s nothing worse than having to wait a half a day to get the results from one SPICE simulation\u00a0 and the hope is that AMI can fix that through behavioral modeling.\u00a0 Mentor has been an active part of this process with Arpad Muranyi, modeling guru and IBIS advocate, being the chair of the IBIS ATM (Advanced Technology Modeling) Task Group<\/a> which created the AMI specification.<\/p>\n

There is quite a bit of interest in AMI to say the least, but there’s probably a few things you should know if you’re looking into these models.\u00a0 As we work with silicon vendors, it’s becoming more clear that SPICE may still be a requirement with AMI.\u00a0 The thing with AMI models is that they expect an analog input waveform. \u00a0 Hopefully this can come from a traditional analog IBIS model, but that may not always be sufficient, especially if you have AC coupling in your channel. \u00a0\u00a0 So now you’ve got SPICE back in the picture to create the analog behavior.\u00a0 So what does AMI buy you then?\u00a0 Well for one, if you’re doing SPICE simulations, most likely the majority of your simulation time is consumed by the receiver and modeling\u00a0 it’s equalization behavior (that’s a broad generalization but I’d say it’s typically true from the models I’ve seen).\u00a0 The AMI model can replace all that time intensive simulation in SPICE.\u00a0 It can also be used to model the clock recovery, something you’re not going to get out of your SPICE simulations either.\u00a0 Also, once the channel has been characterized with the analog waveform, you can now start to do some real number crunching.\u00a0 Instead of being limited to a few thousand bits of simulation time, you can quickly get millions of bits of data in a matter of minutes. \u00a0 So there is definite value, even if it isn’t exactly what you might have initially expected from this modeling standard.<\/p>\n

The first availability of AMI support will be right around the corner in Mentor’s analysis tools- delivered first in HyperLynx SI.\u00a0 If you want to see the first incarnation of this, check out the following webinar <\/a>that we’re delivering with Xilinx <\/a>on Jan 28th –Multi-GHz Channel Analysis using HyperLynx and Xilinx’ IBIS-AMI Models<\/a>.\u00a0 We’ll be covering the Xilinx Virtex 5 AMI models and showing some pretty cool outputs that you can get from this design kit in HyperLynx, including 3D eye density plots.<\/p>\n

\"Top\"3D<\/p>\n","protected":false},"excerpt":{"rendered":"

If you do any kind of multi-gigabit SerDes design, you’ve probably come across the acronym, AMI – Algorithmic Modeling Interface.\u00a0\u00a0…<\/p>\n","protected":false},"author":71697,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[13],"tags":[1014,1015,1057,1063,1067,1068,1085,1086,1087,1115,1122,1141,1148,1152,1154],"industry":[],"product":[],"coauthors":[],"class_list":["post-9198","post","type-post","status-publish","format-standard","hentry","category-news","tag-ami","tag-atm","tag-eye-diagram","tag-hyperlynx","tag-ibis","tag-ibis-50","tag-modeling","tag-models","tag-multi-gigabit","tag-serdes","tag-spice","tag-v5","tag-virtex-5","tag-webinar","tag-xilinx"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/9198","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/71697"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=9198"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/9198\/revisions"}],"predecessor-version":[{"id":10277,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/9198\/revisions\/10277"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=9198"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=9198"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=9198"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=9198"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=9198"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=9198"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}