{"id":6199,"date":"2019-04-18T12:05:40","date_gmt":"2019-04-18T19:05:40","guid":{"rendered":"https:\/\/blogs.mentor.com\/jimmartens\/?p=6199"},"modified":"2026-03-27T09:32:33","modified_gmt":"2026-03-27T13:32:33","slug":"automated-electrical-design-rule-checking-for-faster-time-to-market-part-2","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2019\/04\/18\/automated-electrical-design-rule-checking-for-faster-time-to-market-part-2\/","title":{"rendered":"Automated Electrical Design Rule Checking for Faster Time to Market \u2013 Part 2"},"content":{"rendered":"

In part one of this 2-part blog series, we examined how electrical Design Rule Checking (DRCs) uncovers violations that often go undetected, leading to higher quality designs on aggressive schedules.\u00a0 This second blog looks at more advanced capabilities in HyperLynx DRC in PADS Professional, including analyzing signal transitions, timing on high-speed nets and signal and power integrity.\u00a0 To read part one, click here<\/a>.<\/em><\/p>\n

Analyzing Signal Transitions from Layer-to-Layer<\/u><\/strong><\/p>\n

The \u2018vertical reference plane change\u2019 rule looks at instances of signal transitioning from one layer to another. While changing planes is a common design practice to accommodate today\u2019s densely-packed PCB layouts, care must be taken to reduce risk of common mode radiation. Frequently, capacitors or stitching vias are placed to allow for continuous current return path. This rule determines whether those conditions are met. The designer runs the rule on their previously defined GPIO object list to specify constraints for plane changes. If there are violations, further exploration could show that they occur on different pins of the device header. The need for addressing those violations would depend on what the headers are used for and the purpose of those pins.<\/p>\n

Timing on High Speed Nets<\/u><\/strong><\/p>\n

The next rule that the designer runs is the \u2018delay and links matching\u2019 rule. Timing on high-speed nets is incredibly important for proper functionality, especially on DDR nets. If DDR signals do not reach their destination with proper timing constraints, the memory will not work properly. Timing issues occur for a multitude of reasons including transmission line propagation delay due to layer stack up, dielectric properties and trace routing. As delay issues are often due to unique physical properties of a PCB, it is an important parameter the designer must take into account. As DDR nets often fall victim to delay issues, the designer creates another object\u2019s list containing the DDR nets.<\/p>\n

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Object\u2019s list – Containing the DDR nets<\/figcaption><\/figure>\n

For this specific test, the designer checks the delay matching, the length matching, or both. One of the powerful features of HyperLynx DRC is automatically calculating necessary values from the layer stack up information. The designer specifies a new created DDR net object list as the target for this rule. In the customizable parameters, the designer can request the DRC tool to calculate the propagation delay from the stack up, by selecting \u2018Yes\u2019 for the parameter. The designer then executes the rule with the custom settings. If there are violations, PADS Professional will display the exact affected nets highlighted in red, and the reference net highlighted in green.<\/p>\n

Signal and Power Integrity:<\/u><\/strong><\/p>\n

HyperLynx DRC has advanced rules that aid in identifying possible signal and power integrity issues. In DDR Design that uses fly-by topology, stub length is important for proper functionality.<\/p>\n