![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/55\/2017\/03\/GettyImages-493795876-520x347.jpg\")
To deal with today\u2019s high-speed technologies, many design engineers deploy a design process that includes simulation, but what they\u2019re finding might not be enough.<\/p>\nTo deal with today\u2019s high-speed technologies, many design engineers deploy a design process that includes simulation, but what they\u2019re finding might not be enough.<\/p>\n
There are many situations where SI analysis alone won\u2019t detect common problems<\/strong><\/a>. For example, SI analysis tools assume signals have a continuous return path. This assumption won\u2019t help when that signal crosses a split plane or void area. These tools won\u2019t catch physical geometries like this.<\/p>\n Fortunately, there are solutions. PADS HyperLynx DRC<\/strong><\/a> delivers innovative, rules-based analysis that identifies common problems that a simulation-only methodology won\u2019t catch. Not only will DRC alert you to nets crossing gaps (splits and voids), it will also find isolated metal islands, vertical reference plane changes, crosstalk coupling, differential impedance, long stubs, and too many vias on a net.<\/p>\n Most of us are hesitant to use a new tool because of the startup time necessary to learn it, so we made PADS HyperLynx DRC easy to deploy. A built-in wizard prompts you though all setup, and will have you running these complex design checks in no time. Try it for yourself! Request a free trial.<\/strong><\/a><\/p>\n Think of how you identify these types of issues today. Best case \u2013 you spend time reviewing the design in painstaking detail, looking for the issues mentioned above. As the designs get larger and denser, this detailed search become almost impossible. Worst case \u2013 you identify the issues in the lab while testing your prototype. This necessitates a revision, costing you time and money.<\/p>\n