{"id":512,"date":"2012-03-06T12:55:11","date_gmt":"2012-03-06T19:55:11","guid":{"rendered":"https:\/\/blogs.mentor.com\/hyperblog\/?p=512"},"modified":"2026-03-27T09:18:23","modified_gmt":"2026-03-27T13:18:23","slug":"put-the-pieces-in-place-for-serdes-success","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2012\/03\/06\/put-the-pieces-in-place-for-serdes-success\/","title":{"rendered":"Put the Pieces in Place for SERDES Success"},"content":{"rendered":"<p>Interconnect loss modeling?\u00a0 Check.\u00a0<br \/>\nSignal conditioning modeling?\u00a0 Check.\u00a0<br \/>\nAbility to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?\u00a0 Oooh&#8230;. that&#8217;s a tough one.\u00a0 Check!<br \/>\nAbility to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?\u00a0 Wow!\u00a0 Check.<br \/>\n3D via modeling?\u00a0 Check!<br \/>\nHyperLynx 8.2 is fully equipped to handle every SERDES problem you can throw at it.\u00a0 Really, any\u00a0signal integrity\u00a0problem you can throw at it.\u00a0 Power integrity too.<\/p>\n<p>In general, SERDES designs are a lot easier to implement than parallel busses.\u00a0 You have a smaller number of problems to worry about, but the problems that are there are considerable.\u00a0 They are basically problems of fast edges and low margins.\u00a0 The fast edges require careful attention to detail in all aspects of the layout, and bring about the need to analyze pieces of the interconnect that could be ignored with slower edges, most notably vias.\u00a0 And the low margins necessitate a greater understanding of when the bus will actually fail.\u00a0 So in order to be successful in the analysis of these busses, care must be taken to include everything that is needed to understand the limits.<\/p>\n<p>Read more about it in my recent article in New Electronics magazine:\u00a0<br \/>\n<a href=\"http:\/\/www.newelectronics.co.uk\/electronics-technology\/the-challenges-of-designing-high-speed-interfaces-at-the-board-level\/40549\/\" target=\"_blank\" rel=\"noopener\">http:\/\/www.newelectronics.co.uk\/electronics-technology\/the-challenges-of-designing-high-speed-interfaces-at-the-board-level\/40549\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Interconnect loss modeling?\u00a0 Check.\u00a0 Signal conditioning modeling?\u00a0 Check.\u00a0 Ability to simulate multiple S-parameter models for things like connectors and packages&#8230;<\/p>\n","protected":false},"author":71672,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[13],"tags":[1011,1016,1019,48,1054,1063,1073,1100,1115],"industry":[],"product":[],"coauthors":[],"class_list":["post-512","post","type-post","status-publish","format-standard","hentry","category-news","tag-3d-via","tag-ber","tag-channel-analysis","tag-crosstalk","tag-equalization","tag-hyperlynx","tag-interconnect-loss","tag-pre-emphasis","tag-serdes"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/512","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/71672"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=512"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/512\/revisions"}],"predecessor-version":[{"id":10314,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/512\/revisions\/10314"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=512"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=512"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=512"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=512"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=512"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=512"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}