The basic formula for characteristic impedance is:<\/p>\n We can see that it’s made up of the capacitive and inductive properties of the trace.\u00a0 So what does this mean to a board designer? You can impact what the impedance of your traces are, largely based on your stackup design.\u00a0 Here are the main things in the stackup that we can use to control the impedance: dielectric thickness, dielectric constant, and trace width<\/strong>.\u00a0 The copper thickness can also play a part but it is less significant.<\/p>\n With dielectric thickness, we’re trying to determine how far away the trace should be placed from it’s reference layer(s).\u00a0 This is often ground for ideal situations but it could be a power layer as well.<\/p>\n We also need to consider that the trace could be a microstrip (on the outer layer of the board) or a stripline (on an inner layer with references above and below the trace) structure.\u00a0 There are other types of structures such as dual stripline or buried microstrip but I just wanted to provide an example of 2 of the primary types of structures you’ll deal with.\u00a0\u00a0 In both examples, when you decrease the dielectric thickness, you’ll decrease the impedance.\u00a0 Likewise, increasing thickness will increase impedance.\u00a0 Generally speaking, for the same dielectric thickness and trace width, you’ll have a higher impedance on a microstrip line than you will for a stripline because of the additional capacitance provided in the stripline structure.<\/p>\n The other important piece relative to the dielectric is the dielectric constant.\u00a0 Standard FR4 material in most PCBs will have a relative dielectric constant (commonly seen as Er or Dk – these symbols are interchangeable) on average of about 4.3 but if you choose a dielectric with a much lower Er, it will cause the impedance to increase.\u00a0 Similarly, if you were to increase the Er, it would cause the impedance to go down.\u00a0 The leaver you have to control the Er is the laminate you choose for the stackup design.\u00a0 If you want to see your options in more exotic materials, check out Isola <\/a>or Rogers<\/a> who are just two options of several in the laminate material industry.<\/p>\n The last factor that can play a major part in trace impedance is the trace width.\u00a0 If you increase the trace width, the impedance will go down.\u00a0 If you decrease the width, the impedance will go up.<\/p>\n So what makes all these properties behave the way they do?\u00a0 You can trace most of the changes down to how the capacitance is calculated. Looking at the equation for capacitance in a parallel plate, we can see there is dependency on dielectric constant, separation between the plates (d), as well as the area (A).<\/p>\n We can see that if the Er changes, that has a direct relationship on the capacitance.\u00a0 And going back to the characteristic impedance equation, it has an inverse relationship on impedance (e.g. Er goes up \u2192 impedance goes down).\u00a0 We can also see that as the separation between the two parallel plates increases, it has an inverse relationship on the capacitance, which means it has a direct relationship with the impedance (e.g. separation goes up\u00a0\u2192 capacitance goes down\u00a0\u2192 impedance goes up).\u00a0\u00a0 And lastly, the area changes based on the trace width, so if the trace width goes up, capacitance goes up, which means the impedance goes down.<\/p>\n There are stackup planning tools in HyperLynx as well as Expedition which can simplify your life when it comes to impedance planning.\u00a0 It can be as simple as entering a target impedance for a layer given a certain stackup and HyperLynx will tell you the the trace width you need.\u00a0 Or you can enter a width and it will give you an impedance on any given layer.<\/p>\n I’ll leave you with some final thoughts on impedance control from a practical perspective.\u00a0 For most companies, if you design impedance controlled boards, your manufacturer is going to adjust whatever values you give them to hit the target impedances based on the materials they have on-hand.\u00a0 You may specify 6 mil width for traces and they may do 5.6 mils in production, but the end result that matters is that they are meeting your target impedance.\u00a0 One trick to give your manufacturer more ability to hit impedance goals is to specify slight differences in trace width for your targeted impedances, especially when it comes to differential impedance (I haven’t even touch on differential impedance here so I’ll save that for another post ).\u00a0 For instance, on Layer 4 of your stackup, you may have a 50 ohm target impedance which results in a 5 mil trace width for single ended traces, and a 100 ohm differential impedance with 5 mil traces on the same layer.\u00a0 For the single ended traces, just put 5.1 mils into your design and for the differential, make it 4.9 mils.\u00a0 That will allow them to target both impedances for you independent of each other without having to make compromises to either target impedance.<\/p>\n![\"Characteristic](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/47\/2010\/06\/impedance2.png\")
![\"Stripline](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/47\/2010\/06\/stripline_microstrip.png\")
![\"Capacitance\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/47\/2010\/06\/capacitance.png\")
![\"stackup\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/47\/2010\/06\/stackup-520x330.png\")
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