{"id":23,"date":"2020-04-27T12:54:57","date_gmt":"2020-04-27T16:54:57","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/pcbflow\/?p=23"},"modified":"2026-03-27T09:45:54","modified_gmt":"2026-03-27T13:45:54","slug":"solder-mask-coverage-violations-and-how-to-prevent-them","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2020\/04\/27\/solder-mask-coverage-violations-and-how-to-prevent-them\/","title":{"rendered":"Solder Mask Coverage Violations and how to prevent them"},"content":{"rendered":"\n

During my years in the PCB pre-production world, I\u2019ve seen the challenge of preparing design data for production in a way that is both cost-effective and will improve production yields. Most PCB fabricators agree that if PCB designers would take into consideration the fabrication constraints and their impact on the fabrication process, they would be surprised at how easy it could be to improve their designs<\/a>. <\/p>\n\n\n\n

Solder mask preparation is one of the bigger challenges in this field,\nand solder mask coverage provides an excellent example of the impact that\ndesign practices have on successful fabrication. <\/p>\n\n\n\n

Let\u2019s have a look!<\/p>\n\n\n\n

Solder Masks and Clearances<\/strong><\/h2>\n\n\n\n

In order to protect the copper traces of a printed circuit board\n(PCB) from the environment and from undesired electrical contacts (solder\nbridging) during assembly, a thin, non-conductive layer called solder mask<\/em> (SM) is applied to the outer layers of the board.\nAfter the mask is applied, openings in the solder mask \u2013 known as clearances<\/em> \u2013 must be created wherever components are\ngoing to be soldered. Those openings are defined in the SM layer on each side of\nthe board and taken into consideration during all stages of PCB design,\nfabrication and assembly. <\/p>\n\n\n\n

When analyzing a board for manufacturability, special attention needs to be paid to the solder mask, since faulty clearances may result in assembly process defects, which, in turn, will result in the scrapping of assembled boards,<\/del> and in reduced project profitability.<\/p>\n\n\n\n

What is an \u201cSM Coverage Violation\u201d?<\/strong><\/h2>\n\n\n\n

Solder mask clearances should be large enough to securely expose\ncopper pads for soldering. On the other hand, they should be small enough in\norder to keep away from copper traces or other copper features that should not\nbe exposed. In dense designs, these two requirements often contradict,\nrequiring layout engineers to compromise and optimize.<\/p>\n\n\n\n

The distance between the solder mask clearance and the unexposed\ncopper is called \u201cSM Coverage\u201d.  An\nexample appears in the figure below.<\/p>\n\n\n\n

When insufficient SM coverage exists \u2013 in which the SM clearance\nis closer to unexposed copper than specified in constraint values \u2013 this is\nconsidered an \u201cSM Coverage Violation\u201d, which requires the attention of the\nlayout engineer.<\/p>\n\n\n\n

\"solder<\/figure>\n\n\n\n

In addition to layout considerations, PCB fabricators need to consider the potential inaccuracies caused during the photo-lithographic process used to create SM clearances after the solder mask is applied. These inaccuracies might cause solder mask clearances to slightly change their shape and\/or location. Thus, during PCB fabrication analysis, a minimum SM coverage distance is set as a constraint parameter \u2013 this parameter must be set in accordance with the procedures employed by the fabricator. <\/p>\n\n\n\n

Why it is important to detect SM coverage violation in the early stage of layout?<\/strong><\/h2>\n\n\n\n

When a SM Coverage violation is detected during a pre-production\nfabrication analysis, the usual procedure is to reshape (shrink or partly\nshave) the faulty clearance in order to increase the distance between the clearance\nand the exposed copper. Besides being tedious and error-prone, this process\ncompromises the clearance quality. <\/p>\n\n\n\n

If these violations are detected early in the design process, the layout engineer can more easily remediate them.  This is where PCBflow<\/strong> comes in.  PCBflow is Siemens\u2019 online <\/a>DFM<\/a> (Design-for-Manufacturing) tool .  Developed for use by board designers in startups and SMEs, PCBflow provides immediate feedback on design errors and violations, thereby reducing the number of board spins which can cut costs and reducing time-to-market. <\/p>\n\n\n\n

PCBflow issues alert indications when errors or violations\noccur.  For example, it provides\nnotifications of SM coverage violations in the layout stage, allowing the layout\nengineer to find an optimal solution \u2013 for instance, by using thinner traces,\nor by rerouting the traces away from pads.<\/p>\n\n\n\n

The platform runs in a secured cloud environment, so you can\nrest assured that your IP is fully protected. <\/p>\n\n\n\n

Sign up and try it out at www.pcbflow.com<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"

During my years in the PCB pre-production world, I\u2019ve seen the challenge of preparing design data for production in a…<\/p>\n","protected":false},"author":70060,"featured_media":25,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[12,17],"tags":[],"industry":[],"product":[693],"coauthors":[1894],"class_list":["post-23","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-learning-resources","category-tips-tricks","product-pcbflow"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2020\/04\/solder-mask.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/23","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/70060"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=23"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/23\/revisions"}],"predecessor-version":[{"id":10801,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/23\/revisions\/10801"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media\/25"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=23"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=23"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=23"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=23"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=23"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=23"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}