One of the basic concepts of signal integrity is maintaining impedance. Whether a design will be successful or not can depend on how detailed the impedance planning has been in the design process.<\/p>\n
Most nets run on multiple layers, often with a large number of trace segments, which makes the planning for impedance matching a difficult feat. Yet even more difficult is making sure your layout engineer sticks to the plan. And the task doesn\u2019t get any easier if you\u2019re trying to do it all: design, layout, and verification.<\/p>\n
When we consider differential pairs, the problem gets twice as hard as the impedance depends not only on trace widths but also on separation.<\/p>\n
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\nAs you can imagine, manually checking all the segments on all the differential pairs in an entire design can be back-breaking work. Foregoing impedance checking is also not a feasible option, for how else would you know that your design really works?<\/p>\n
With the HyperLynx DRC Free Edition<\/a>, or any other HyperLynx DRC configuration, you can use the differential-pair impedance rule to do the checking for you.<\/p>\n Just create an object list, enter rule parameter values (such as target impedance, tolerance for deviation from the target, etc.), and click Run. HyperLynx DRC will highlight all the violations and give you a list that you can click through to look at each violation. To learn more about the rule, check out this video<\/a>.<\/p>\n
![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/47\/2018\/05\/Blog-Diff-Impedance-2.png\")
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