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<\/a><\/p>\nDDR3 and DDR4 designs, for instance, are becoming very common.\u00a0 They employ a number of interface-specific mechanisms for maintaining performance, such as write-leveling and data bus inversion or DBI. Validating these interfaces requires consideration of on-chip timing, slew-rate derating to accurately characterize the on-board timing, and even taking into account the effects of the power distribution network on timing and signal quality.<\/p>\n
High-speed serial or SERDES interfaces are pushing the limits of PCB performance.\u00a0 In order to properly characterize these signals at higher frequencies, advanced 3D solvers must be used to model pieces of the interconnect like vias, connectors, and chip breakouts. Combining those models with S-parameter models and trace models properly is essential to accurately characterizing the channel.\u00a0 And, new methods have emerged to simulate the channel and predict its performance down to very low BER (bit error rate) levels.<\/p>\n
At this year\u2019s PCB Forums<\/a>, presenters will demonstrate all of the great technology in HyperLynx and how it applies to your PCB designs. Whether you\u2019re an advanced designer or newer and still learning, and regardless of what solutions you currently utilize, PCB Forums has sessions for you. Find a location near you and reserve your seat today!<\/a><\/p>\n In the meantime, here are a couple of product demos of the SERDES simulation capabilities in HyperLynx:<\/p>\n