{"id":1575,"date":"2015-06-24T08:00:17","date_gmt":"2015-06-24T15:00:17","guid":{"rendered":"https:\/\/blogs.mentor.com\/hyperblog\/?p=1575"},"modified":"2026-03-27T09:24:31","modified_gmt":"2026-03-27T13:24:31","slug":"using-data-bus-inversion-to-mitigate-simultaneously-switching-noise","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2015\/06\/24\/using-data-bus-inversion-to-mitigate-simultaneously-switching-noise\/","title":{"rendered":"Using Data Bus Inversion to Mitigate Simultaneously Switching Noise"},"content":{"rendered":"

This is the third post in a three part series that examines the problem of SSN and explores methods of reducing SSN in your designs. Click to read Part 1<\/a> and Part 2<\/a> of this 3 part blog series.<\/em><\/p>\n

In the first installment of our blog series on Simultaneously Switching Noise<\/a>, we went through an overview of SSN and explained its relevance to high-speed parallel busses such as DDR4. In the second post<\/a>, we examined the effects of a poorly designed Power Distribution Network (PDN) on SSN and signal integrity. This final post will elaborate further on the Data Bus Inversion (DBI) option introduced at the conclusion of the previous post.<\/p>\n

DBI is an optional feature in DDR4.\u00a0 If DBI is enabled, then when the driver (controller during a write or DRAM during a read) is sending out data on a lane, it counts the number of \u201c0\u201d (logic low) bits.\u00a0 If the number of bits driving \u201c0\u201d in the lane is five or more, then the entire byte is inverted, and a ninth bit indicating DBI is asserted low.\u00a0 This ensures that out of the 8 DQ bits and the 9th<\/sup> DBI bit, at least five bits are \u201c1\u201d during any given transaction.\u00a0 This also ensures that out of the entire data lane, the maximum total number of signals transitioning is either five 1\u2019s to 9 1\u2019s or vice-versa.\u00a0 There can never be a situation where all bits go from 0 to 1 or from 1 to 0.<\/p>\n

So, if we run the same data bus with data patterns which would be the output of the DBI logic, we get the waveform for DQ0 in Figure 1.<\/p>\n

\"Figure<\/a>
Figure 1: DBI processed bit patterns with improved PDN<\/figcaption><\/figure>\n

The eye-height for DQ0 in this case is over 315mV, which surpasses all the other conditions.\u00a0 Now, since DBI is data dependent, the benefits of DBI may vary and need to be analyzed before implementation.<\/p>\n

Thank you for following our blog series on SSN\u2014we hope you find this information valuable and share your thoughts in the comments. With a good design of the PDN, and possibly selecting the DBI feature in DDR4, SSN shouldn\u2019t be a bother in your design. If you\u2019d like to learn more about SSN and similar challenges, check out our white paper \u201cDDR4 Board Design and Signal Integrity Challenges,\u201d<\/a> which was recently nominated for the DesignCon Best Paper Award.<\/p>\n","protected":false},"excerpt":{"rendered":"

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