{"id":11417,"date":"2026-01-27T11:24:20","date_gmt":"2026-01-27T16:24:20","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/?p=11417"},"modified":"2026-03-27T09:48:33","modified_gmt":"2026-03-27T13:48:33","slug":"etch","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2026\/01\/27\/etch\/","title":{"rendered":"Etch effects exposed: discover where your copper really goes"},"content":{"rendered":"\n

Until recently, I thought that people who believed in rectangular traces were about as common as people that believe in square waves and a flat earth.\u00a0 Recently, though, I was asked about it and came to realize that it\u2019s not as clear as I initially thought it was\u2014not only for newbies, but in general.\u00a0 Over the last 25 years, I\u2019ve acquired a good number of books on PCB design and signal integrity and you wouldn\u2019t know from reading most of the industry literature that traces were anything but rectangular and that etching remained somewhat mysterious. Interesting, right?<\/p>\n\n\n\n

The stripline cross section in FIGURE 1<\/em> is from the Z-planner Enterprise software<\/a>.\u00a0 Among other things, it shows that the base of a trace, facing the core dielectric, is wider than the side of the trace that faces the prepreg.\u00a0 As such, the trace trapezoids face both up and down in a multilayer stackup<\/a>.\u00a0 There\u2019s no relationship to the layer number or whether the trace is on the top or bottom half of the board.\u00a0 For this reason, I and others\u2014but not everyone\u2014avoid using terms like \u201ctop\u201d or \u201cbottom\u201d as it regards trapezoidal traces.<\/p>\n\n\n\n

In the dimensions shown in FIGURE 1<\/em>, the w1 value at the base of the trapezoid is the value that hardware teams and fabricators exchange when talking about trace widths and spacing (s), but it\u2019s important to know that actual, fabricated boards won\u2019t have quite that much copper.\u00a0 As traces are etched from top to bottom, the etching chemical (\u201cetchant\u201d) remains in contact with the prepreg side of the trace longer than the core side. This makes the prepreg side of the trace narrower than the core side and gives the trace a trapezoidal cross section.\u00a0 In this blog we\u2019ll discuss the reasons for this fabrication phenomenon<\/a> and the implications for impedance.<\/p>\n\n\n

\n
\"stackup
FIGURE 1. The trapezoidal shape of inner-layer traces, shown in a stripline cross section, where w2 is narrower than w1. (Image from Z-planner Enterprise software<\/a>.)<\/strong><\/figcaption><\/figure><\/div>\n\n\n

Inner-Layer Etching<\/h3>\n\n\n\n

Etching inner layers involves cleaning the copper on both sides of the piece of laminate, applying a photoresist, exposing the photoresist to create the inner layer pattern, developing the resist, etching away the unwanted copper, and removing the etch resist. This process is automated in most shops and the chemistry is automatically monitored. As a result, the accuracy and repeatability is quite good. It is possible to etch inner layer traces using this process to an accuracy of \u00b10.5 mils. This accuracy control helps keep impedance within the tolerances required for transmission lines. <\/p>\n\n\n\n

After cores are cleaned, FIGURE 2<\/em> shows a blue light-sensitive film or photo-imageable \u201cresist\u201d that is applied by heat and pressure to the metal surfaces of the core. The film is sensitive to ultraviolet light. \u00a0If you ever tour a fab shop, the room where photo-resist is handled uses \u201cyellow light\u201d to prevent inadvertent exposure of the resist. The filters remove the wavelength of light that would affect the resist coating.<\/p>\n\n\n

\n
\"resist
FIGURE 2. Blue resist film is placed on both sides of an inner-layer core prior to imaging, UV exposure, and subsequent etching.<\/strong><\/em><\/figcaption><\/figure><\/div>\n\n\n

The GERBER or ODB++ data for the part is used to plot film that depicts the traces and pads of the board design. The photo tools or artwork include the copper features. This film is used to place an image on the resist.<\/p>\n\n\n\n

Inner-layer film is a \u201cnegative\u201d image of the copper features, meaning that the copper patterns left behind after processing the core correspond to the transparent areas on the film. Core panels are exposed to high-intensity ultraviolet light that serves to harden or \u201cpolymerize\u201d the film resist, creating an image of the circuit pattern\u2014very similar to a slide-negative and a photograph.<\/p>\n\n\n\n

The exposed core is then processed through a chemical \u201cdeveloper\u201d that removes the resist from areas that were not hardened by the UV light.\u00a0 Next, the copper is chemically etched from the core in all areas not covered by the remaining blue dry-film resist. After etching, the developed dry-film resist is chemically removed from the panel, leaving just the copper features exposed on the panel. It\u2019s even a bit more nuanced than we\u2019ve alluded to so far.\u00a0 <\/p>\n\n\n\n

As FIGURE 3<\/em> shows, the actual sides of a trace will be curved and there is an etching \u201cundercut\u201d below the blue resist.<\/a>\u00a0 Remember that w1 is the dimension that hardware teams and fabricators use to describe trace widths.\u00a0 R is the width of the resist that the fabricator uses.\u00a0 And the ledge under the resist is the undercut, u<\/em>.\u00a0 Ideally, R, w2, and w1 would be equal.\u00a0 The closer that a fabricator can get to this, the better, and good fabricators work hard to achieve this.<\/p>\n\n\n

\n
\"undercut
FIGURE 3. The actual sides of a trace will be curved and there is an etching \u201cundercut\u201d below the blue resist.<\/em><\/strong><\/figcaption><\/figure><\/div>\n\n\n

The gap between resist areas is removed evenly at first and then in a progressively cup-shaped fashion until the center area between traces is broken through to the exposed core dielectric, which opens progressively as the etchant goes to work in and under the resist as the side wall is gradually removed through increased exposure. \u00a0The amount of time that the copper is exposed to the etchant determines the final shape of the copper features, as illustrated in FIGURE 4<\/em>.<\/p>\n\n\n\n

When the resist width (R) is equal to the base of the trapezoid (w1), this would be ideal etching.\u00a0 In FIGURE 4<\/em>, this corresponds to the 140 second etching scenario.\u00a0 Note too that if R is less than w1, as in the cases up to 125 seconds, the copper features or traces are underetched.\u00a0 In the case where the copper is exposed to the etchant for 165 seconds, the copper is overetched.\u00a0 The times here are for this specific example, where cupric chloride was used as an etchant, targeting 3.0-mil line and space patterns, using 1.0-mil resist on 1-oz (1.35-mil) copper foil.<\/p>\n\n\n\n

\"How
FIGURE 4. Using a 3-mil resist, with a 3-mil target for w1, these images show that the amount of time that the copper is exposed to the etchant determines the final shape and widths of the copper features.<\/em><\/strong><\/figcaption><\/figure>\n\n\n\n

Etch Factor<\/h3>\n\n\n\n

From the parameters in FIGURE 3<\/em>, there are two descriptive measures of the etching process\u2014undercutting and etch factor.\u00a0 Undercutting is well defined.\u00a0 It\u2019s the average overhang of resist after top width reduction.\u00a0 Hardware teams don\u2019t really need to worry about the width of the resist, but the \u201cundercut\u201d term and concept are useful.\u00a0 Obviously, the goal is to minimize the U parameter.<\/p>\n\n\n

\n
\"undercut<\/figure><\/div>\n\n\n

\u201cEtch factor\u201d is quite a bit murkier.  Some define it as being proportional to copper thickness, t, and inversely related to the difference between w1 and w2, the width difference in the trapezoid.  But depending on whom you\u2019re talking to, these relationships may be inverted or use different parameters.  And even worse, some tools define etch factor as an angle, with values ranging from 45-90 degrees for upward-facing trapezoids and from 270-315 degrees for downward-facing trapezoids.  Since industry standards don\u2019t exist, we now live in a world where we need to track and understand how each tool vendor implemented what we all call \u201cetch factor.\u201d<\/p>\n\n\n\n

A relationship that I find to be intuitive is shown in FIGURE 5<\/em>. It would be nice if we could agree on a definition like this, where x<\/em> (\u201cetchback\u201d) is the difference between w1 and w2, and \u201cetch factor\u201d is defined as the degree of etchback per thickness.\u00a0 This definition is used in HyperLynx<\/a>, Xpedition<\/a>, and Z-planner Enterprise<\/a>.<\/p>\n\n\n

\n
\"etch
FIGURE 5. Proposed definitions for \u201cetchback\u201d and \u201cetch factor,\u201d where x (etchback) is the difference between w1 and w2, and etch factor is defined as the degree of etchback per thickness.<\/figcaption><\/figure><\/div>\n\n\n

Fabricator Data<\/h3>\n\n\n\n

Average suppliers typically maintain roughly 0.25 mils of etchback for half-ounce copper and 0.5 mils of etchback for 1-oz. copper, respectively.    <\/p>\n\n\n\n

Advanced PCB manufacturers<\/a> can bring these numbers to 0.17 mils for half-ounce copper and 0.45 mils for 1-ounce copper.<\/p>\n\n\n\n

Plated Layers<\/h3>\n\n\n\n

I hate to open up another can of worms to discuss outer layers, but I will briefly address the subject for completeness.\u00a0 In short, outer layers are even more complicated\u2014particularly when multiple plating steps are used and when copper reduction techniques are used to keep the surface copper thickness down.\u00a0 Sometimes, microstrip traces are anvil shaped rather than trapezoidal shaped, but more commonly\u00a0 they look more like a \u201cmesa,\u201d borrowing a term from geology, with the top plated section almost vertical and then the trapezoidal cross-section at the bottom. (I.e., a rectangle on top of a trapezoid, with the rectangle representing the plated copper.) \u00a0The Z-planner Enterprise software<\/a> estimates the cross-sectional area of the plated trapezoid for impedance calculations.<\/p>\n\n\n\n

Plated layers often have other challenges, including the fact that there may be 1, 2, or even 3 plating passes.  Some designs are plated 1x and end up exactly 1-mil thick, while other boards have 1x plating and are considerably thicker. <\/p>\n\n\n\n

Impedance Implications<\/h3>\n\n\n\n

Let\u2019s consider an \u201caverage\u201d PCB fabricator, where a 1-oz. stripline layer has 0.5 mils of etchback and compare the impedance results against a trace where etchback is ignored. In FIGURE 6, the left image with the blue border assumes a rectangular<\/em> trace cross section.\u00a0 The image on the right includes the 0.5 mils of etchback<\/em> for a single-ended transmission line targeting 50 ohms and a differential pair targeting 100 ohms.\u00a0 As you can see, the single-ended impedance difference is 1.25 ohms and the differential-impedance difference is about 2.5 ohms.\u00a0 <\/p>\n\n\n\n

Could your design live with such a difference?\u00a0 It depends on a lot of factors, some that you control and some that are random.\u00a0 You don\u2019t directly control Dk variation or copper-thickness variation from nominal, for example, but you can specify impedance at +\/- 10 percent.\u00a0 The difference that we\u2019re showing here would be stacked on top of Dk variation, copper-thickness variation, and any other variation in fabrication.\u00a0 In short, you\u2019re giving up ohms right out of the gate, which is not a good design practice.<\/p>\n\n\n\n

\"rectangular
FIGURE 6. The left image with the blue border assumes a rectangular trace cross section. The image on the right includes the 0.5 mils of etchback for a single-ended transmission line targeting 50 ohms and a differential pair targeting 100 ohms. (Simulated with Z-planner Enterprise, using Siemens\u2019 HyperLynx 2D field solver.)<\/figcaption><\/figure>\n\n\n\n

Discover more<\/h3>\n\n\n\n
\n\n\n\n
\"copper<\/a><\/figure>
\n

Go beyond copper etch.<\/strong><\/p>\n\n\n\n

Explore the relationship between copper roughness and signal integrity. Discover 10 critical things you need to know about copper roughness and its impact on board costs during your stackup design process.<\/p>\n\n\n\n

\n
View webinar<\/a><\/div>\n<\/div>\n<\/div><\/div>\n\n\n\n<\/div>\n\n\n\n

Z-planner Enterprise free trial<\/h2>\n\n\n
\n
\"PCB<\/figure><\/div>\n\n\n

I would like to encourage your to look into this relationship more yourself. Our\u00a0free online trial of Z-planner Enterprise<\/a> has tools which help you to explore and experiment with various trace width values as shown above. The trial grants you full access to the entire suite of stackup design materials, including access to our line of dielectric stackup materials. It provides you the opportunity to perform all of this comparison completely free.<\/p>\n","protected":false},"excerpt":{"rendered":"

Etching inner layers involves cleaning the copper on both sides of the piece of laminate, applying a photoresist, exposing the photoresist to create the inner layer pattern, developing the resist, etching away the unwanted copper, and removing the etch resist. This process is automated in most shops and the chemistry is automatically monitored. As a result, the accuracy and repeatability is quite good. It is possible to etch inner layer traces using this process to an accuracy of \u00b10.5 mils. This accuracy control helps keep impedance within the tolerances required for transmission lines. <\/p>\n","protected":false},"author":115516,"featured_media":11425,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[12,17],"tags":[2093,2094,113,115,1995],"industry":[],"product":[998],"coauthors":[2051],"class_list":["post-11417","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-learning-resources","category-tips-tricks","tag-copper","tag-etch-effects","tag-pcb-design","tag-pcb-stack-up","tag-z-planner-enterprise","product-z-planner-enterprise"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/vlcsnap-00063.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11417","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/115516"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=11417"}],"version-history":[{"count":2,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11417\/revisions"}],"predecessor-version":[{"id":11427,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11417\/revisions\/11427"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media\/11425"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=11417"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=11417"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=11417"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=11417"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=11417"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=11417"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}