{"id":11374,"date":"2026-02-03T10:01:00","date_gmt":"2026-02-03T15:01:00","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/?p=11374"},"modified":"2026-03-27T09:48:35","modified_gmt":"2026-03-27T13:48:35","slug":"insertion-loss","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2026\/02\/03\/insertion-loss\/","title":{"rendered":"Minimizing insertion loss: Why understanding trace width is critical at high frequencies"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\"><a><strong>Material matters<\/strong><\/a><\/h2>\n\n\n\n<p>An engineer asked me recently about the relationship between trace width and insertion loss while adjusting dielectric height to maintain a 50 Ohm single-ended impedance.&nbsp;<\/p>\n\n\n\n<p>At a high level, there are 5 variables at work here, including <a href=\"https:\/\/webinars.sw.siemens.com\/en-US\/stackup-design-for-signal-integrity-engineers\/\" target=\"_blank\" rel=\"noopener\">trace width<\/a>, <a href=\"https:\/\/webinars.sw.siemens.com\/en-US\/copper-roughness-and-si\/\" target=\"_blank\" rel=\"noopener\">copper weight<\/a>, <a href=\"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2022\/11\/15\/what-materials-are-used-in-pcbs\/\">dielectric height<\/a>, <a href=\"https:\/\/webinars.sw.siemens.com\/en-US\/pcb-stackup-design-material\/\" target=\"_blank\" rel=\"noopener\">Dk, and Df<\/a>.&nbsp; Include frequency and resin content, and we\u2019re really talking about 7 variables. Then there are stripline vs. microstrip configurations, which change things a bit, as well as % copper (which impacts prepreg thickness), and copper roughness.&nbsp; We\u2019ll keep things simple, for discussion\u2019s sake, and address some of these factors in future columns.<\/p>\n\n\n\n<p>Lossy transmission-line effects become significant <a href=\"https:\/\/resources.sw.siemens.com\/en-US\/e-book-signal-integrity-basics\/\" target=\"_blank\" rel=\"noopener\">signal integrity concerns<\/a> at clock frequencies above roughly 1 GHz and for interconnect lengths that exceed 12 inches. Assuming that we&#8217;re talking striplines, and grabbing data from a Megtron 6 (G) stackup I was looking at today, we\u2019ll use an insertion loss comparison between two different trace width\/dielectric height combinations. (Dks are similar, but a little bit different\u2014depending on resin content.)<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Example Design<\/strong><\/h3>\n\n\n\n<p>From <a href=\"https:\/\/na.industrial.panasonic.com\/products\/electronic-materials\/circuit-board-materials\/lineup\/megtron-series\/series\/127603\" target=\"_blank\" rel=\"noopener\">Panasonic\u2019s Megtron 6<\/a> (G) tables, an example 8-layer stackup provides a convenient illustration (modified for this blog post):<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Layer 3\u2014Narrow trace width, thinner dielectrics:<ul><li>Width=2.66 mils<\/li><\/ul><ul><li>Cores at 3 mils (single ply 1078 glass); half-oz. copper<\/li><\/ul>\n<ul class=\"wp-block-list\">\n<li>Pressed prepregs at 2.64 mils (single ply)<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Layer 6\u2014Wider trace, thicker dielectrics:<ul><li>Width=5.15 mils<\/li><\/ul><ul><li>Cores at 5 mils (dual-ply1078 glass); half-oz. copper<\/li><\/ul>\n<ul class=\"wp-block-list\">\n<li>Pressed prepregs at 5.64 mils (dual-ply 1078 glass)<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Electrical characteristics for dielectrics:<ul><li>Cores:&nbsp; Dk = 3.64&nbsp; (RC=54%); Df = 0.004<\/li><\/ul>\n<ul class=\"wp-block-list\">\n<li>Prepregs:&nbsp; Dk = 3.4&nbsp; (RC=63%; 1078 glass); Df = 0.003<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n<p>At 10 GHz, column X&nbsp; in Figures 1 and 2 show insertion loss computed at 0.91 dB\/in. for the 2.66-mil wide trace on layer 3 and 0.62 dB\/in. for the 5.15 mil line on layer 6, aligning with the conventional wisdom that a narrower trace width results in increased signal attenuation.3<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"556\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1-1024x556.png\" alt=\"8 layer PCB stackup visualization\" class=\"wp-image-11375\" srcset=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1-1024x556.png 1024w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1-600x326.png 600w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1-768x417.png 768w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1-900x489.png 900w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-1.png 1252w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><strong>Figure 1: &nbsp;8-layer example stackup using <a href=\"https:\/\/eda.sw.siemens.com\/en-US\/pcb\/valor\/stackup-design-high-speed\/resources\/\" target=\"_blank\" rel=\"noopener\">Z-planner software <\/a>shows a 2.66-mil wide trace width on layer 3 and a 5.15-mil trace width on layer 6\u2014with differential impedances at 100 ohms. We will use this to examine our overall insertion loss.<\/strong><\/figcaption><\/figure><\/div>\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"772\" height=\"803\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-2.png\" alt=\"wider stackup trace values\" class=\"wp-image-11376\" style=\"width:562px;height:auto\" srcset=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-2.png 772w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-2-577x600.png 577w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-2-768x799.png 768w\" sizes=\"auto, (max-width: 772px) 100vw, 772px\" \/><figcaption class=\"wp-element-caption\"><strong>Figure 2: &nbsp;Zoomed-in view of signals on layers 3 and 6.&nbsp; The wider trace on layer 6 shows a significantly lower insertion loss than the narrower trace width on layer 3.<\/strong><\/figcaption><\/figure><\/div>\n\n\n<h3 class=\"wp-block-heading\"><strong>Key Insertion Loss Components<\/strong><\/h3>\n\n\n\n<p>In addition to <a href=\"https:\/\/webinars.sw.siemens.com\/en-US\/copper-roughness-and-si\/\" target=\"_blank\" rel=\"noopener\">copper roughness, which I covered in a recent webinar<\/a>, there are two other components of insertion loss:&nbsp; resistive loss, the subject of this blog, and <a href=\"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2022\/07\/05\/choosing-the-right-laminate-for-your-pcb-design\/\">dielectric loss<\/a>.&nbsp;<\/p>\n\n\n\n<p><em>Resistive Loss:<\/em>\u00a0 From DC through frequencies up to a few MHz, the current in a trace moves through the entire cross-sectional area of the trace.\u00a0 At higher frequencies, however, current flows along the perimeter of a line rather than uniformly across the entire cross section.\u00a0 As a result, the series resistance of the signal and return path conductors increases with the square root of frequency as the effective cross section of the interconnect path is reduced.\u00a0 This type of loss is often referred to as \u201cskin effect.\u201d\u00a0<\/p>\n\n\n\n<p><em>Dielectric Loss: &nbsp;<\/em>The second important loss mechanism is dielectric loss, which is simply the conversion of electrical energy from the alternating electric field into heat.&nbsp; Dielectric loss is often specified in decibels per inch, increases with frequency, and varies inversely with a material\u2019s \u201cdissipation factor\u201d or Df\u2014which is a function of the material\u2019s resin type and molecular structure.&nbsp; Depending on resin content, \u201cstandard loss\u201d FR-4 materials have Dfs ranging from 0.0015-0.015.&nbsp; <\/p>\n\n\n\n<p>Lower Df values equate to more of the output signal getting to its destination, as well as higher material costs, as compared to standard-loss materials.&nbsp; Since we used similar dielectrics on both signal layers in our example, we shouldn\u2019t expect the dielectric loss component to be much different between the narrow trace on layer 3 and the wider trace on layer 6.&nbsp; We can confirm this by using the Loss Viewer in Z-planner software to examine the contributions of conductor loss and dielectric loss to the overall insertion loss across these layers. Layer 3 results for the w=2.66 mil case are shown in <strong><em>Figure 3.<\/em><\/strong><\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"960\" height=\"678\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-3.png\" alt=\"total loss within a stackup\" class=\"wp-image-11377\" srcset=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-3.png 960w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-3-600x424.png 600w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-3-768x542.png 768w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-3-900x636.png 900w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><figcaption class=\"wp-element-caption\"><strong>Figure 3: The Loss Viewer shows a breakdown of all contributors to Total loss (0.91 dB\/in. at 10GHz) and resistive loss from skin effect (0.54 dB\/in.) for layer 3.<\/strong><\/figcaption><\/figure><\/div>\n\n\n<p>Here we can see that dielectric loss is only contributing 0.18 dB\/in., while resistive loss from skin effect) is contributing a full 0.54 dB\/in.\u2014a full 3x the dielectric-loss contribution! Of course, we would want to multiply insertion-loss numbers by trace lengths to produce total channel losses, which is shown in columns Y and Z in <strong><em>Figure 2.<\/em><\/strong><\/p>\n\n\n\n<p><strong><em>Figure 4<\/em><\/strong> shows the same plot for the 5.5 mil trace on layer 6.&nbsp;<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"960\" height=\"678\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-4.png\" alt=\"PCB insertion loss viewer showing skin effect\" class=\"wp-image-11378\" srcset=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-4.png 960w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-4-600x424.png 600w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-4-768x542.png 768w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/Material-Matters-figure-4-900x636.png 900w\" sizes=\"auto, (max-width: 960px) 100vw, 960px\" \/><figcaption class=\"wp-element-caption\"><strong>Figure 4: The Loss Viewer shows a breakdown of all contributors to Total loss (0.62 dB\/in. at 10GHz) and resistive loss from skin effect (0.33 dB\/in.) for layer 6.<\/strong><\/figcaption><\/figure><\/div>\n\n\n<p>Here we can see that our dielectric loss hasn\u2019t changed, while skin effect has dropped significantly\u2014to just 0.33 dB\/in.&nbsp; Of course, the thicker dielectrics would result in a bigger overall board thickness, but if you\u2019re hunting for eliminating the last few dBs from an interconnect budget, it\u2019s helpful to have gained this insight early in the design process.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Conclusions<\/strong><\/h3>\n\n\n\n<p>Some say that <a href=\"https:\/\/resources.sw.siemens.com\/en-US\/technology-overview-optimize-pcb-density-and-accelerate-routing-with-area-rules\/\" target=\"_blank\" rel=\"noopener\">trace width<\/a> isn\u2019t a big deal when it comes to insertion loss, but here we learned that <em>significantly wider trace widths<\/em> can be a great lever for reducing insertion loss.&nbsp; One of the costs associated with significantly wider traces is that the board will be thicker and proportionately more expensive.&nbsp; This, in fact, is a common technique for high-speed backplanes where insertion loss is a big concern, and you can afford to spend a bit more.<\/p>\n\n\n\n<p>We could go a good bit further with this example, looking at higher-loss but lower-priced laminates.&nbsp; We could also explore the effect of copper roughness and resin content.&nbsp;<\/p>\n\n\n\n<p>Megtron 6 (G), represents just one alternative in the range of dielectric-loss possibilities among the various laminates on the market.&nbsp; For an actual design, you may want to <a href=\"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/2025\/05\/29\/stackup-materials\/\">make material tradeoffs in a stackup design tool <\/a>and then specifically discuss the tradeoffs with your board vendor.&nbsp;<\/p>\n\n\n\n<p>I greatly encourage you to explore this relationship within your stackups with our&nbsp;<a href=\"https:\/\/trials.sw.siemens.com\/en-US\/trials\/z-planner-enterprise\/\" target=\"_blank\" rel=\"noreferrer noopener\">free online trial of Z-planner Enterprise<\/a>. It grants you full access to the Loss Viewer as well as our line of dielectric stackup materials. It provides you the opportunity to perform all of this comparison completely free. <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Material matters An engineer asked me recently about the relationship between trace width and insertion loss while adjusting dielectric height&#8230;<\/p>\n","protected":false},"author":115516,"featured_media":11388,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[12,17],"tags":[1750,1072,2039,1125],"industry":[341],"product":[998],"coauthors":[2051],"class_list":["post-11374","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-learning-resources","category-tips-tricks","tag-dfm","tag-impedance","tag-insertion-loss","tag-stackup","industry-electronics-semiconductors","product-z-planner-enterprise"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/65\/2025\/06\/futuristic-circuit-board_medium.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11374","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/115516"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=11374"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11374\/revisions"}],"predecessor-version":[{"id":11404,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/11374\/revisions\/11404"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media\/11388"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=11374"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=11374"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=11374"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=11374"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=11374"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=11374"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}