If you\u2019ve ever designed a PCB<\/a>, you know that some parts of the process can feel like magic, especially when it comes to power delivery systems (PDS) also known as power distribution networks (PDNs). One of the more debated topics is where to put decoupling capacitors on a PCB. Should you place them as close as possible to components? Spread them evenly? Or just cram as many as you can fit?<\/p>\n\n\n\n While attending many industry conferences the last few years, I have participated in many insightful and at times \u201cpassionate and colorful\u201d discussions with many of the industry\u2019s top subject matter experts in electronics systems designs. In these discussions, when the topic of PDS or PDNs unfolds, they always involve capacitor values, quantities, and their physical locations within their respective circuits on the PCB. From general rules of thumb to OEM application guidelines, or by lessons learned from actual testing, there is no shortage of philosophies and or suggestions when it comes to where to put decoupling capacitors on a PCB. Yet, no matter who or where the information is obtained from, nor what \u201cbest practice\u201d is suggested to follow, the commonality is to establish a well-balanced PCB stackup<\/a> where the configuration contains tightly coupled power and ground [reference] layer pair(s) situated in and or throughout the stackup. This, along with a thorough power analysis\/simulation of your design is key to creating a successful PDS or PDNs within the PCB. This has never been more evident to me while I sat in on Lee Ritchey\u2019s<\/a> recent technical presentation on Power Delivery System Design<\/em> at PCB West 2024. His technical insights are truly gold, in my opinion! Let\u2019s dig into to best practices and design considerations, and what the real-world implications are.<\/p>\n\n\n\n Capacitors on a PCB aren\u2019t just there to \u201clook good.\u201d They\u2019re essential for stabilizing power delivery by storing and releasing charge during high-speed switching events. Think of them as mini-batteries that provide a quick energy boost to keep your ICs happy when demand spikes. But here\u2019s the thing: their effectiveness isn\u2019t just about their specs\u2026it\u2019s also about where and how you place them.<\/p>\n\n\n\n You might think, \u201cJust stick the capacitors next to the chip, and you\u2019re done.\u201d And while that\u2019s a popular rule of thumb and or an industry best practice, it\u2019s not always that simple.<\/p>\n\n\n\n Take power planes, for example. If your PCB has closely spaced (tightly coupled) power and ground planes, let\u2019s say 4 mils apart, then capacitor location matters much less than you\u2019d expect. Why? Because the planes themselves provide some of the necessary capacitance and spread the charge efficiently.<\/p>\n\n\n\n Now contrast that with a board where the planes are farther apart. Suddenly, the inductance between the capacitor and the chip becomes a bottleneck, and placing capacitors strategically becomes crucial.<\/p>\n\n\n\n During Lees\u2019 technical session, he shared a real-world example from a 10 Gbps line card design. This high-speed board had thousands of pins, dense components, and serious power demands. Placing capacitors directly under a 2,000-pin BGA (ball grid array) chip was avoided. Why? Because cramming capacitors under the BGA would\u2019ve made assembly and rework extremely complex and or nearly impossible. Instead, they distributed the capacitors around the board, ensuring they were accessible and easy to assemble while maintaining performance.<\/p>\n\n\n\n Another case shared by Lee involved a simple I\/O module where just four capacitors were used\u2014two 1 \u00b5F ceramics and two 100 \u00b5F tantalums. Interestingly, these capacitors didn\u2019t even play a major role at the design\u2019s operating frequencies. The PCB\u2019s tightly coupled power planes carried the workload, proving that sometimes less is more when the design is right.<\/p>\n\n\n\n Here\u2019s a myth that might surprise you: ultra-low inductance capacitors aren\u2019t always better.<\/strong> Sure, they sound fancy, but their benefits can disappear if they\u2019re connected through high-inductance mounting structures. In many cases, using common capacitor package sizes like 0402 or 0603 with well-designed vias is a smarter and more cost-effective choice. Surprisingly, common best practices of bypass capacitor placement, such as close as possible, underneath each part, by every power pin, and with traces to power pins are not very accurate. <\/p>\n\n\n\n So, how do you ensure your capacitor placement doesn\u2019t become the week point of your design? Here are some practical tips I\u2019d like to pass along from Lee\u2019s technical session:<\/p>\n\n\n\n Where to put decoupling capacitors on a PCB might not seem exciting, but it\u2019s a make-or-break factor for your PCB\u2019s power delivery system, which is a critical part of any electronic systems design. The good news? By understanding the science behind placement and learning from shared insights and real-world examples by industry experts like Lee Ritchey, you can design boards that are not only reliable but also easier to manufacture and maintain. I\u2019d like to thank my dear friend and industry expert Lee Ritchey of Speeding Edge for allowing me to share insights (golden nuggets) from his technical session. Remember, every design is unique and requires the upmost due diligence, but with these principles in mind, you\u2019ll be well on your way to mastering the art (and science) of where to put decoupling capacitors on a PCB.<\/p>\n\n\n\n Looking for more PCB design best practices? <\/p>\n\n\n\nThe basics: what do capacitors do?<\/h2>\n\n\n\n
Why where to put decoupling capacitors on a PCB matters<\/h2>\n\n\n\n
Real-world lessons<\/h2>\n\n\n\n
Busting some myths<\/h2>\n\n\n\n
Practical tips for where to put decoupling capacitors on a PCB<\/h2>\n\n\n\n
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